57.8.7 SPI CRC Generation and Checking

The SPI offers the possibility to compute and check a CRC while receiving a frame. To enable the CRC check, the CRC Enable (CRCEN) bit must be set to ‘1’ in FLEX_SPI_MR.

The SPI CRC register (FLEX_SPI_CRCR) configures the frame length using the Frame Length (FRL) field and the CRC size using the CRC Size (CRCS) bit.

The CRC checksum uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 standard: x16 + x15 + x2 + 1.

It is possible to define a frame header length with the Frame Header Length (FRHL) field, and a frame header can be included or excluded from CRC calculation depending on the Frame Header Excluded (FHE) bit configuration. In case of continuous read frames, the Continuous Read Mode (CRM) bit defines if the frame header is sent only at the beginning of the first frame or at every frame. The CRC Error (CRCERR) flag in FLEX_SPI_SR indicates any failed CRC check.

It is possible to configure the SPI to receive or not CRC and/or Header as a classic data by configuring FLEX_SPI_CRCR.DCRX and FLEX_SPI_CRCR.DHRX. When CRC and/or Header is configured not to be received as data, upon receiving the Header and/or CRC, the RDRF flag does not rise and the FLEX_SPI_RDR register is not updated with the received value.