3 Compare Mode

Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one of the following events can occur based on the configuration of the MODE control bits:

  • Toggle the CCPx output and clear TMRx.
  • Toggle the CCPx output without clearing TMRx.
  • Set the CCPx output.
  • Clear the CCPx output.
  • Generate a pulse output.
  • Generate a pulse output and clear TMRx.

In Compare mode, Timer1 acts as a timebase or as a counter. For example, if Timer1 is configured so that the comparison match point occurs every 50 ms, CCP hardware will generate an output event at a repeatable interval. If Timer1 is configured as a counter, CCP hardware will generate an output event based on the number of times Timer1 records an event.

Compare mode hardware can also clear Timer1 after certain events occur. This feature can be useful when operating Timer1 as a fixed time base.

Figure 3-1 shows a simplified diagram of the compare operation.

Figure 3-1. Compare Mode Operation Block Diagram