3.5 Compare Mode Configuration

Compare Mode Initialization Routines shows the CCP and Timer1 Initialization routines for Compare mode. The CCPRx register pair is loaded with value 0x3CB0. When Timer1 reaches 0x3CB0, which occurs approximately every 50 ms, CCP hardware generates a pulsed output and clears Timer1.

Compare Mode Initialization Routines 

void CCP1_Initialize(void)
{
    CCP1CON = 0x8B;              // MODE Pulse-clear-timer
    CCPR1H = 0x3C;               // When TMR1 = 0x3CB0 = 50 ms
    CCPR1L = 0xB0;
}

void TMR1_Initialize(void)
{
    T1GCON = 0x00;
    T1GATE = 0x00;
    T1CLK = 0x01;                // CS FOSC/4
    TMR1H = 0x00;
    TMR1L = 0x00;
    PIR1bits.TMR1IF = 0;         // Clear IF flag   
    T1CON = 0x01;                // CKPS 1:1; ON enabled
}