3.2 Program/Verify Commands

Once a device has entered ICSP Program/Verify mode (using either high-voltage or LVP entry), the programming host device may issue commands to the microcontroller, each eight bits in length. The commands are summarized in Table 3-1 and are used to erase or program the device based on the location of the Program Counter (PC).

Some 8-bit commands also have an associated data payload (such as Load PC Address and Read Data from NVM).

If the host device issues an 8-bit command byte that has an associated data payload, the host device is responsible for sending an additional 24 clock pulses (e.g., three 8-bit bytes) to send or receive the payload data associated with the command.

The payload field size is compatible with many 8-bit SPI-based systems. Within each 24-bit payload field, the first bit transmitted is always a Start bit, followed by a variable number of Pad bits, followed by the useful data payload bits and ending with one Stop bit. The useful data payload bits are always transmitted MSb first.

When the programming device issues a command that involves a host to the microcontroller payload (e.g., Load PC Address), the Start, Stop and Pad bits must all be driven by the programmer, as defined by the data column in Table 3-1. When the programming host device issues a command that involves the microcontroller to host payload data (e.g., Read Data from NVM), the Start, Stop and Pad bits must be treated as ‘don't care’ bits and the values may be ignored by the host.

When the programming host device issues an 8-bit command byte to the microcontroller, the host must wait a specified minimum amount of delay (which is command-specific) prior to sending any additional clock pulses (associated with either a 24-bit data payload field or the next command byte).

Table 3-1.  ICSP™ Command Set Summary
Command NameCommand ValuePayload ExpectedDelay after CommandData/Note
Binary (MSb … LSb)Hex
Load PC Address1000 000080YesTDLYPayload Value = PC
Bulk Erase Program Memory0001 100018YesTERABThe payload is used to identify the regions that need to be bulk erased.
Row Erase Program Memory1111 0000F0NoTERASThe row addressed by the MSbs of the PC is erased; LSbs are ignored.
Load Data for NVM0000 00J000/02Yes – Data InTDLYData is loaded to the data latch addressed by the LSbs of the PC; MSbs are ignored.

J = 0:

PC is unchanged

J = 1:

PC = PC + 1 after writing

Read Data from NVM1111 11J0FC/FEYes – Data OutTDLYData output ‘0’ if code-protect is enabled.

J = 0:

PC is unchanged

J = 1:

PC = PC + 1 after reading

Increment Address1111 1000F8NoTDLYPC = PC + 1
Begin Internally Timed Programming1110 0000E0NoTPINTCommits latched data to NVM (self-timed).
Begin Externally Timed Programming1100 0000C0NoTPEXTCommits latched data to NVM (externally timed). After PTEXT, the End Externally Timed Programming command must be used.
End Externally Timed Programming1000 001082NoTDISMust be issued within required time delay (TPEXT) after the Begin Externally Timed Programming command.
Important: All clock pulses for both the 8-bit commands and the 24-bit payload fields are generated by the host programming device. The microcontroller does not drive the ICSPCLK line. The ICSPDAT signal is a bidirectional data line. For all commands and payload fields, except for the Read Data from NVM payload, the host programming device continuously drives the ICSPDAT line. Both the host programmer device and the microcontroller must latch the received ICSPDAT values on the falling edge of the ICSPCLK line. When the microcontroller receives the ICSPDAT line values from the host programmer, the ICSPDAT values must be valid a minimum of TDS before the falling edges of ICSPCLK and must remain valid for a minimum of TDH after the falling edge of ICSPDAT. See Figure 3-5.
Figure 3-5. Clock and Data Timing