27.3.3 Interrupts
| Offset | Name | Vector Description | Conditions |
|---|---|---|---|
| 0x00 | NMI | Non-Maskable Interrupt | Generated on CRC failure |
When the interrupt condition occurs, the OK flag in the Status register (CRCSCAN.STATUS) is cleared to '0'.
An interrupt is enabled by writing a '1' to the respective Enable bit (NMIEN) in the Control A register (CRCSCAN.CTRLA), but can only be disabled with a system Reset. An NMI is generated when the OK flag in CRCSCAN.STATUS is cleared and the NMIEN bit is '1'. The NMI request remains active until a system Reset, and can not be disabled.
A non-maskable interrupt can be triggered even if interrupts are not globally enabled.