9.5.4 Interrupt Control

Offset: 0x03
Reset: 0x00
Property: -

Bit 76543210 
Access R/W 
Reset 0 

Bit 0 – EEREADY EEPROM Ready Interrupt

Writing a '1' to this bit enables the interrupt which indicates that the EEPROM is ready for new write/erase operations.

This is a level interrupt that will be triggered only when the EEREADY flag in the INTFLAGS register is set to zero. Thus, the interrupt should not be enabled before triggering an NVM command, as the EEREADY flag will not be set before the NVM command issued. The interrupt should be disabled in the interrupt handler.