3 LAN8650/1 Support for Time Synchronization

The LAN8650/1 includes hardware features to enable clock synchronization and to use the synchronized clock to synchronize external signals and capture timestamps from external events. Figure 3-1 provides an overview of these hardware features. This application note presents a simple application concept; as a result, not all of the time synchronization features listed in the datasheet are used.

Figure 3-1. Time Synchronization Features of the LAN8650/1

Wall Clock

The wall clock or local clock is a set of internal counter registers which are used by software to synchronize the device to an external clock source. The wall clock provides the timestamps used for inbound and outbound packets in the MAC and in event timestamp unit. It is also used by the event generator to generate synchronized signals.

In the the LAN8650/1 the wall clock is a 94-bit counter where:
  • The 48 upper bits [93:46] represent seconds.
  • The 30 lower bits [45:16] represent nanoseconds. This field resets to 0 at the end of each second.
  • The lowest 16 bits [15:0] of the timer count sub‑nanoseconds. This field resets to 0 at the end of each nanosecond. It is not accessible by register read or write.

Software can directly update the seconds and nanoseconds portions of the wall clock by writing to registers. Most implementations will directly modify the wall clock once, at the start of clock synchronization.

The clock will increase in value every tick of the local oscillator by the value contained in increment registers. For this device, the value is nominally set to 40 ns corresponding to the specified 25 MHz input clock.

Once the initial value is written, software then tunes the wall clock so that it synchronizes to the clock source. It does not change the wall clock time directly, but uses one of two means to modify the behavior. It can either modify the increment for each tick of the local clock, down to fractions of a nanosecond where needed, or it can perform a single adjustment to increment or decrement the wall clock. The exact method used can be determined by the designer of the synchronization algorithm.

Event capture and event generation use all 48 seconds bits and all 30 nanoseconds bits. Packet timestamps accessed using the built‑in features of the SPI protocol will use the least significant 2 or 32 seconds bits depending on the selected timestamp format.

Packet Pattern Matcher

The LAN8650/1 includes a packet pattern matcher that enables accurate timestamping. When using the round trip delay calculation of Equation 2-1, it is assumed that the delay is equal in both directions. As described above, the PLCA elastic buffer contributes a variable length delay during transmission. In the LAN8650/1, the transmit pattern matcher signals the timestamp unit that the end of the SFD has been transmitted by the PHY, so that the time stamp is captured at this time, instead of using the time the SFD leaves the MAC. This ensures a consistent internal delay when transmitting packets. To ensure that the receive timestamps are made with a similar delay, the receive packet pattern matcher is used to trigger the timestamping at the end of the SFD in receive packets.

Packet Timestamping

When configured to do so, the packet timestamp unit captures a timestamp when signaled by the pattern matcher. The SPI MAC-PHY protocol enables configuration of timestamps and provides them to the controller as follows:
  • Receive packet timestamps:
    • Receive packet timestamps for all incoming packets are enabled by setting the Frame Timestamp Enable (FTSE) bit of OA_CONFIG0.
    • The Receive Timestamp Added (RTSA) bit will be set in the footer along with the Start Valid (SV) bit.
    • The timestamp will be prepended to the packet data and delivered in the first data block of the packet.
    • The Receive Timestamp Parity bit (RTSP) of the footer will be '1' if the timestamp parity is odd, else it will be '0'.
    • The timestamp width (32 or 62 bits) is selected using the Frame Timestamp Select (FTSS) bit in the Configuration 0 Register (OA_CONFIG0).
  • Transmit packet timestamps:
    • A timestamp is requested for a particular packet by setting the Timestamp Capture (TSC) field of the data header of the first block of data transmitted for that packet.
    • The TSC is a two-bit field, which indicates which of the Transmit Timestamp Capture High/Low register pairs should contain the timestamp.
    • When the frame is transmitted, the timestamp will be captured, placed into desired Transmit Timestamp Capture register pair, and set the appropriate Transmit Timestamp Capture Available (TTSCAA, TTSCAB, TTSCAC ) status bit in the Status 0 (OA_STATUS0) register.
    • A successful timestamp capture can be used to trigger an interrupt, if desired.
    • The timestamp capture registers can be read like any other registers on the device, using SPI control transactions.
Important:

The LAN8650/1 is not configured for correct timestamp capture after reset, but the default configuration set by all Microchip drivers ensures proper configuration. See the LAN8650/1 Configuration Application Note for details, especially if writing your own driver. Software must additionally request transmit and receive timestamps via the SPI protocol and process the resulting timestamps.

Event Timestamping

The event capture unit can simultaneously monitor up to four events and capture the wall clock time at which the configured event occurs. Each event has its own configuration register, which can select the source from DIOA0-3 or either the transmit or receive pattern matcher. When DIO pins are used, they must also be configured as event capture inputs in the PADCTRL register.

To enable efficient use of SPI bandwidth, all resulting status and timestamps are available in a group of sequentially accessed registers. This allows for use of the auto‑increment feature of the SPI control protocol to burst read all of the required registers in a single message.

Synchronized Event Generation

There are four configurable event generators, each of which can generate a single edge or configurable width pulse from the same wall clock used for timestamp generation. The generated signals can be routed to pins DIOA0-3 so they can be used to synchronize external devices. The routing is controlled by the PADCTRL register.

1 Pulse Per Second

The device can provide a one pulse-per-second (1PPS) clock synchronized to the wall clock. This signal can be provided on pin DIOA4. The pulse width can be configured between 640 ns and 20.48 μs. The 1PPS signal is output on pin DIOA4 when configured in the PADCTRL register. A 1PPS signal is often used to monitor the synchronization of the clock or as a reference for other PLLs.