13 Glossary

Table 13-1. Glossary
Term	Definition
Arrival time	Actual time in nanoseconds when data arrives at a sink pin when considering the propagation delays across the path.
Asynchronous	Two signals that are not related to each other. Signals not related to the clock are usually asynchronous.
Capture edge	The clock edge that triggers the capture of data at the end point of a path.
Clock	A periodic signal that captures data into sequential elements.
Critical path	A path with the maximum delay between a starting point and an end point. In the presence of a clock constraint, the worst critical path between registers in this clock domain is the path with the worst slack.
Data timing analysis	The standard method for verifying design functionality and performance. Both pre-layout and post-layout timing analysis can be performed via the SDF interface.
Exception	See timing exception.
Explicit clock	Clock sources that can be traced back unambiguously from the clock pin of the registers they deserve, including the output of a DLL or PLL.
Filter	A set of limitations applied to object names in timing analysis to generate target specific sets.
Launch edge	The clock edge that triggers the release of data from a starting point to be captured by another clock edge at an end point.
Minimum period	Timing characteristic of a path between two registers. It indicates how fast the clock will run when this path is the most critical one. The minimum period value takes into consideration both the skew and the setup on the receiving register.
Parallel paths	Paths that run in parallel between a given source and sink pair.
Path	A sequence of elements in the design that identifies a logical flow starting at a source pin and ending at a sink pin.
Path details	An expansion of the path that shows all the nets and cells between the source pin and the sink pin.
Path set	A collection of paths.
Paths list	Same as path set.
Post-layout	The state of the design after you run Layout. In post-layout, the placement and routing information are available for the whole design.
Potential clock	Pins or ports connected to the clock pins of sequential elements that the Static Timing Analysis (STA) tool cannot determine whether they are is enabled sources or clock sources. This type of clock is generally associated with the use of gated clocks.
Pre-layout	The state of the design before you run Layout. In pre-layout, the placement and routing information are not available.
Recovery time	The amount of time before the active clock edge when the de-activation of asynchronous signals is not allowed.
Removal time	The amount of time after the active clock edge when the de-activation of asynchronous signals is not allowed.
Required time	The time when data must be at a sink pin to avoid being in violation.
Requirement	See timing requirement.
Scenario (timing constraints scenario)	Set of timing constraints defined by the user.
Setup time	The time in nanoseconds relative to a clock edge during which the data at the input to a sequential element must remain stable.
Sink pin	The pin located at the end of the timing path. This pin is usually the one where arrival time and required time are evaluated for path violation.
Skew	The difference between the clock insertion delay to the clock pin of a sink register and the insertion delay to the clock pin of a source register.
Slack	The difference between the arrival time and the required time at a specific pin, generally at the data pin of a sequential component.
Slew rate	The time needed for a signal to transition from one logic level to another.
Source pin	The pin located at the beginning of a timing path.
STA	See static timing analysis.
Standard delay format (SDF)	A standard file format used to store design data suited for back-annotation.
Static timing analysis	An efficient technique to identify timing violations in a design and to ensure that all timing requirements are met. It is well suited for traditional synchronous designs. The main advantages are that it does not require input vectors, and it exclusively covers all possible paths in the design in a relatively short run-time.
Synopsys design constraint (SDC)	A standard file format for timing constraints. Synopsys Design Constraints (SDC) is a Tcl-based format used by Synopsys tools to specify the design intent, including the timing and area constraints for a design. Microsemi SoC tools use a subset of the SDC format to capture supported timing constraints. You can import or export an SDC file from the Designer software. Any timing constraint that you can enter using Designer tools, can also be specified in an SDC file.
Timing constraint	A requirement or limitation on the design to be satisfied during the design implementation.
Timing exception	An exception to a general requirement usually applied on a subset of the objects on which the requirement is applied.
Timing requirement	A constraint on the design usually determined by the specifications at the system level.
Virtual clock	A virtual clock is a clock with no source associated to it. It is used to describe clocks outside the FPGA that have an impact on the timing analysis inside the FPGA. For example, if the I/Os are synchronous to an external clock.
Wire Load Model (WLM)	A timing model used in pre-layout to estimate a net delay based on the fan-out.

Arrival time

Actual time in nanoseconds when data arrives at a sink pin when considering the propagation delays across the path.

Asynchronous

Two signals that are not related to each other. Signals not related to the clock are usually asynchronous.

Capture edge

The clock edge that triggers the capture of data at the end point of a path.

Clock

A periodic signal that captures data into sequential elements.

Critical path

A path with the maximum delay between a starting point and an end point. In the presence of a clock constraint, the worst critical path between registers in this clock domain is the path with the worst slack.

Data timing analysis

The standard method for verifying design functionality and performance. Both pre-layout and post-layout timing analysis can be performed via the SDF interface.

Exception

See timing exception.

Explicit clock

Clock sources that can be traced back unambiguously from the clock pin of the registers they deserve, including the output of a DLL or PLL.

Filter

A set of limitations applied to object names in timing analysis to generate target specific sets.

Launch edge

The clock edge that triggers the release of data from a starting point to be captured by another clock edge at an end point.

Minimum period

Timing characteristic of a path between two registers. It indicates how fast the clock will run when this path is the most critical one. The minimum period value takes into consideration both the skew and the setup on the receiving register.

Parallel paths

Paths that run in parallel between a given source and sink pair.

Path

A sequence of elements in the design that identifies a logical flow starting at a source pin and ending at a sink pin.

Path details

An expansion of the path that shows all the nets and cells between the source pin and the sink pin.

Path set

A collection of paths.

Paths list

Same as path set.

Post-layout

The state of the design after you run Layout. In post-layout, the placement and routing information are available for the whole design.

Potential clock

Pins or ports connected to the clock pins of sequential elements that the Static Timing Analysis (STA) tool cannot determine whether they are is enabled sources or clock sources. This type of clock is generally associated with the use of gated clocks.

Pre-layout

The state of the design before you run Layout. In pre-layout, the placement and routing information are not available.

Recovery time

The amount of time before the active clock edge when the de-activation of asynchronous signals is not allowed.

Removal time

The amount of time after the active clock edge when the de-activation of asynchronous signals is not allowed.

Required time

The time when data must be at a sink pin to avoid being in violation.

Requirement

See timing requirement.

Scenario (timing constraints scenario)

Set of timing constraints defined by the user.

Setup time

The time in nanoseconds relative to a clock edge during which the data at the input to a sequential element must remain stable.

Sink pin

The pin located at the end of the timing path. This pin is usually the one where arrival time and required time are evaluated for path violation.

Skew

The difference between the clock insertion delay to the clock pin of a sink register and the insertion delay to the clock pin of a source register.

Slack

The difference between the arrival time and the required time at a specific pin, generally at the data pin of a sequential component.

Slew rate

The time needed for a signal to transition from one logic level to another.

Source pin

The pin located at the beginning of a timing path.

STA

See static timing analysis.

Standard delay format (SDF)

A standard file format used to store design data suited for back-annotation.

Static timing analysis

An efficient technique to identify timing violations in a design and to ensure that all timing requirements are met. It is well suited for traditional synchronous designs. The main advantages are that it does not require input vectors, and it exclusively covers all possible paths in the design in a relatively short run-time.

Synopsys design constraint (SDC)

A standard file format for timing constraints. Synopsys Design Constraints (SDC) is a Tcl-based format used by Synopsys tools to specify the design intent, including the timing and area constraints for a design. Microsemi SoC tools use a subset of the SDC format to capture supported timing constraints. You can import or export an SDC file from the Designer software. Any timing constraint that you can enter using Designer tools, can also be specified in an SDC file.

Timing constraint

A requirement or limitation on the design to be satisfied during the design implementation.

Timing exception

An exception to a general requirement usually applied on a subset of the objects on which the requirement is applied.

Timing requirement

A constraint on the design usually determined by the specifications at the system level.

Virtual clock

A virtual clock is a clock with no source associated to it. It is used to describe clocks outside the FPGA that have an impact on the timing analysis inside the FPGA. For example, if the I/Os are synchronous to an external clock.

Wire Load Model (WLM)

A timing model used in pre-layout to estimate a net delay based on the fan-out.

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13 Glossary