In SmartTime, timing paths are organized by clock domains.

You can create and manage custom path sets for timing analysis and tracking purposes.

SmartTime displays the list of paths and path details for all parallel paths.

You can use filters in SmartTime to limit the Path List content (that is, create a filtered list on the source and sink pin names).

After you activate the inter-clock domain checking for a given clock domain CK1, SmartTime detects automatically all other domains CKn with paths ending at CK1.

Output propagation delay is affected by both the capacitive loading on the board and the I/O standard.

The Timing Report allows you to determine whether timing problems exist in your design.

The Timing Violations Report provides a Flat Slack Report centered around constraint violations.

The Constraints Coverage Report contains information about the constraints in the design.

The Datasheet Report shows information about a design’s external characteristics.

The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.

The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.

This tutorial describes how to enter a clock constraint for the 32-bit shift register on SmartFusion2 device.