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Introduction
2 Design Flows with SmartTime
3 Starting and Closing SmartTime
5 SmartTime Toolbar
6.1 SmartTime Analyzer Components
6.2 Analyzing Your Design
6.3 Maximum Delay Analysis View
6.4 Managing Clock Domains
In SmartTime, timing paths are organized by clock domains.
6.5 Managing Path Sets
You can create and manage custom path sets for timing analysis and tracking purposes.
6.6 Displaying Path List Timing Information
6.7 Displaying Expanded Path Timing Information
SmartTime displays the list of paths and path details for all parallel paths.
6.8 Using Filters
You can use filters in SmartTime to limit the Path List content (that is, create a filtered list on the source and sink pin names).
7.1 Understanding Inter-Clock Domain Analysis
7.2 Activating Inter-Clock Domain Analysis
7.3 Displaying Inter-Clock Domain Paths
After you activate the inter-clock domain checking for a given clock domain CK1, SmartTime detects automatically all other domains CKn with paths ending at CK1.
7.4 Deactivating a Specific Inter-Clock Domain
7.5 Changing Output Port Capacitance
Output propagation delay is affected by both the capacitive loading on the board and the I/O standard.
8.1 Types of Reports
8.2 Generating a Timing Report
The Timing Report allows you to determine whether timing problems exist in your design.
8.3 Understanding Timing Reports
8.4 Generating a Timing Violation Report
The Timing Violations Report provides a Flat Slack Report centered around constraint violations.
8.5 Understanding Timing Violation Reports
8.6 Generating a Constraints Coverage Report
The Constraints Coverage Report contains information about the constraints in the design.
8.7 Understanding Constraints Coverage Reports
8.8 Generating a Bottleneck Report
8.9 Understanding Bottleneck Reports - SmartFusion2, IGLOO2, RTG4, and PolarFire
8.10 Generating a Datasheet Report
The Datasheet Report shows information about a design’s external characteristics.
8.11 Understanding Datasheet Reports
8.12 Generating a Combinational Loop Report
The Combinational Loop Report shows all loops found during initialization and reports pins associated with the loop(s) and the location where a loop is broken.
8.13 Understanding Combinational Loop Reports
8.14 Generating a Clock Domain Crossing (CDC) Report
The Clock Domain Crossing (CDC) Report analyzes timing paths that cross from one clock domain (the source clock) to another clock domain (the destination clock). The CDC report helps identify instances where there may be data loss or metastability issues.
10.1 Tutorial 1 - 32-Bit Shift Register with Clock Enable
This tutorial describes how to enter a clock constraint for the 32-bit shift register on SmartFusion2 device.
10.2 Tutorial 2 - False Path Constraints
10.3 GUID-494EC740-A134-461D-9D4F-BBF0809ECE80-high.jpg
12 Tcl Commands
13 Glossary
14 Revision History
Microchip FPGA Support

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.