1.7 Buck Layout Guide

To achieve the best buck output voltage performance, follow the layout recommendations as listed:

  • Place the inductor and capacitor of the buck circuit in the same layer and close to IS1870.
  • Buck trace width must be at least 15 mils.
  • Buck input – See Figure 1-1 and Figure 1-2 for IS1870 pin 29. Place the buck input capacitor (C17) as close as possible to pin 29 (BK1_IN). The buck input routing path sequence is from VBAT to C17, then connect C17 to pin 29. Do not connect VBAT directly to pin 29 without connecting to C17.
  • Buck output – See Figure 1-1 for IS1870 pin 27. The buck output routing path sequence from pin 28 is BK_LX, L3, C12, BK_O and must be as short as possible. Connect the trace of the buck output to the load from C12.
  • Do not place the ground trace under inductor L3 on the top layer.
  • Place the solid ground plane on the second layer. The ground path from C12 to IS1870 EP (exposed) ground must be short and direct without being interrupted by another trace/traces. Place the ground of C12 at least a ground Via to the ground plane to reduce the ground impedance.
Figure 1-1. Recommended Buck Layout Scheme
Figure 1-2. Recommended Routing and Placement of the Buck Circuit

To ensure the buck output voltage quality, the wire wound coil high current inductor is recommended for the buck inductor. The 10 uH wire wound inductor (ZWP-0805-100K) with high IDC and low DCR are recommended. The following figure is an example considered from ZenithTek.

Note: It is recommended not to use Multi-layer Ceramic Inductor (MLCI) as L3 because it may not start up the chip stably. The poor yield rate also affects the quality of voltage.
Figure 1-3. 10 uH Wire Wound Inductor Example