When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
Name:
DDRE
Offset:
0x2D
Reset:
0x00
Property:
When addressing as I/O Register:
address offset is 0x0D
Bit
7
6
5
4
3
2
1
0
DDREn6
DDREn5
DDREn4
DDRE3
DDRE2
DDRE1
DDRE0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bits 0, 1, 2, 3 – DDRE Port E Data
Direction
This bit field
selects the data direction for the individual pins in the Port. When a Port is
mapped as virtual, accessing this bit field is identical to accessing the actual DIR
register for the Port.
Bits 0, 1, 2, 3, 4, 5, 6 – DDREn Port E Data
Direction
This bit field
selects the data direction for the individual pins in the Port. When a Port is
mapped as virtual, accessing this bit field is identical to accessing the actual DIR
register for the Port.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.