4.2.1 Xplained Pro Standard Extension Headers
The Xplained Pro extension headers EXT1, EXT2, and EXT3 offer access to the I/O of the microcontroller to expand the board, for example, by connecting extensions to the board. These headers are based on the standard Xplained Pro extension header specification. The connections are shown in the table below. The headers have a pitch of 2.54 mm.
| EXT1 Pin | ATmega4809 Pin | Function | Shared Functionality |
|---|---|---|---|
| 1 [ID] | — | — | Communication line to the ID chip on an extension board |
| 2 [GND] | — | — | Ground |
| 3 [ADC(+)] | PD2 | ADC0 AIN2 | — |
| 4 [ADC(-)] | PD3 | ADC0 AIN3 | — |
| 5 [GPIO1] | PA2 | GPIO (USART0 XCK) | — |
| 6 [GPIO2] | PA3 | GPIO (USART0 XDIR) | — |
| 7 [PWM(+)] | PC4 | TCA0 WO4 | — |
| 8 [PWM(-)] | PC5 | TCA0 WO5 | — |
| 9 [IRQ/GPIO] | PC6 | GPIO | — |
| 10 [SPI_SS_B/GPIO] | PC7 | GPIO | — |
| 11 [TWI_SDA] | PC2 | TWI0 SDA | EXT2, EXT3, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 12 [TWI_SCL] | PC3 | TWI0 SCL | EXT2, EXT3, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 13 [USART_RX] | PA1 | USART0 RxD | — |
| 14 [USART_TX] | PA0 | USART0 TxD | — |
| 15 [SPI_SS_A] | PA7 | SPI0 SS | — |
| 16 [SPI_MOSI] | PA4 | SPI0 MOSI | EXT2, EXT3, mikroBUS™, EDBG DGI |
| 17 [SPI_MISO] | PA5 | SPI0 MISO | EXT2, EXT3, mikroBUS™, EDBG DGI |
| 18 [SPI_SCK] | PA6 | SPI0 SCK | EXT2, EXT3, mikroBUS™, EDBG DGI |
| 19 [GND] | — | — | Ground |
| 20 [VCC] | — | — | Power for extension board |
| EXT2 Pin | ATmega4809 Pin | Function | Shared Functionality |
|---|---|---|---|
| 1 [ID] | — | — | Communication line to the ID chip on an extension board |
| 2 [GND] | — | — | Ground |
| 3 [ADC(+)] | PD4 | ADC0 AIN4 | — |
| 4 [ADC(-)] | PD5 | ADC0 AIN5 | — |
| 5 [GPIO1] | PE0 | GPIO | — |
| 6 [GPIO2] | PF6 | GPIO/RESET | SW1, DEBUG, EDBG |
| 7 [PWM(+)] | PB4 | TCA0 WO4 | DGI GPIO2 |
| 8 [PWM(-)] | PB5 | TCA0 WO5 | DGI GPIO3, LED0 |
| 9 [IRQ/GPIO] | PB2 | GPIO | DGI GPIO0, SW0 |
| 10 [SPI_SS_B/GPIO] | PB3 | GPIO | DGI GPIO1 |
| 11 [TWI_SDA] | PC2 | TWI0 SDA | EXT1, EXT3, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 12 [TWI_SCL] | PC3 | TWI0 SCL | EXT1, EXT3, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 13 [USART_RX] | PC1 | USART1 RxD | EDBG CDC |
| 14 [USART_TX] | PC0 | USART1 TxD | EDBG CDC |
| 15 [SPI_SS_A] | PE1 | GPIO | — |
| 16 [SPI_MOSI] | PA4 | SPI0 MOSI | EXT1, EXT3, mikroBUS™, EDBG DGI |
| 17 [SPI_MISO] | PA5 | SPI0 MISO | EXT1, EXT3, mikroBUS™, EDBG DGI |
| 18 [SPI_SCK] | PA6 | SPI0 SCK | EXT1, EXT3, mikroBUS™, EDBG DGI |
| 19 [GND] | — | — | Ground |
| 20 [VCC] | — | — | Power for extension board |
| EXT3 Pin | ATmega4809 Pin | Function | Shared Functionality |
|---|---|---|---|
| 1 [ID] | — | — | Communication line to the ID chip on an extension board |
| 2 [GND] | — | — | Ground |
| 3 [ADC(+)] | PD6 | ADC0 AIN6 | mikroBUS™ |
| 4 [ADC(-)] | PD7 | ADC0 AIN7 | — |
| 5 [GPIO1] | PD0 | GPIO | mikroBUS™ |
| 6 [GPIO2] | PD1 | GPIO | mikroBUS™ |
| 7 [PWM(+)] | PF4 | TCB0 WO (TCA0 WO4) | mikroBUS™ |
| 8 [PWM(-)] | PF5 | TCB1 WO (TCA0 WO5) | mikroBUS™ |
| 9 [IRQ/GPIO] | PE2 | GPIO | mikroBUS™ |
| 10 [SPI_SS_B/GPIO] | PE3 | GPIO | — |
| 11 [TWI_SDA] | PC2 | TWI0 SDA | EXT1, EXT2, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 12 [TWI_SCL] | PC3 | TWI0 SCL | EXT1, EXT2, mikroBUS™, CryptoAuthentication™ footprint, EDBG DGI |
| 13 [USART_RX] | PB1 | USART3 RxD | mikroBUS™ |
| 14 [USART_TX] | PB0 | USART3 TxD | mikroBUS™ |
| 15 [SPI_SS_A] | PF2 | GPIO | mikroBUS™ |
| 16 [SPI_MOSI] | PA4 | SPI0 MOSI | EXT1, EXT2, mikroBUS™, EDBG DGI |
| 17 [SPI_MISO] | PA5 | SPI0 MISO | EXT1, EXT2, mikroBUS™, EDBG DGI |
| 18 [SPI_SCK] | PA6 | SPI0 SCK | EXT1, EXT2, mikroBUS™, EDBG DGI |
| 19 [GND] | — | — | Ground |
| 20 [VCC] | — | — | Power for extension board |