12.5 Noise Suppression
Pulses of short duration on SCL/CLK, SDA/IO and RST are ignored if they fall below the threshold of this circuit. These pulses are filtered out, and the device does not enter the reset sequence.
Symbol |
Parameter |
Test Condition |
Min. |
Typ. |
Max. |
Units |
---|---|---|---|---|---|---|
VCC |
High Voltage Limit |
6.0 |
6.5 |
V | ||
VCC |
Low Voltage Limit |
2.0 |
2.4 |
V | ||
tCLK |
Minimum CLK Pulse Width |
Synchronous Operation |
200 |
280 |
ns | |
fCLK |
Minimum CLK Frequency |
Asynchronous Operation |
12 |
14 |
MHz | |
tPOR |
POR Delay |
10 |
70 |
μs | ||
tSUP |
Min. SCL, SDA, RST Pulse |
50 |
200 |
ns |