22.8.3 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DUALE | SINGLEE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DUALE Dual Bit ECC Error Interrupt
This flag is set on the occurrence of a dual bit ECC error. Writing a
‘0’ to this bit has no effect. Reading the ECCADDR register
will clear the Dual Bit Error interrupt flag.
| Value | Description |
|---|---|
| 0 | No dual bit errors have been received since the last clear. |
| 1 | At least one dual bit error has occurred since the last clear. |
Bit 0 – SINGLEE Single Bit ECC Error Interrupt
This flag is set on the occurrence of a single bit ECC error. Writing a
‘0’ to this bit has no effect. Reading the ECCADDR register
will clear the Single Bit Error interrupt flag.
| Value | Description |
|---|---|
| 0 | No errors have been received since the last clear. |
| 1 | At least one single bit error has occurred since the last clear. |