10.2.2 Interrupt Line Mapping

The following table provides details about each of the interrupt lines that is connected to one peripheral instance. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by configuring it in the peripheral’s Interrupt Enable register.

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.

Depending on their criticality, the interrupt requests for one peripheral are either ORed together on the system level, generating one interrupt, or directly connected to the NVIC interrupt lines (see the following table).

An interrupt request sets the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

Table 10-4. NVIC Interrupt Mapping
Module	Source	NVIC Line	Remark
CRU Subsystem	NMI	NMI	Non-Maskable interrupt
RTC	PER	0	Prescalar
	CMP		Compare
	TAMPER		Tamper
	OVF		Overflow
EIC	EXTINT	1	External interrupt
FREQM	DONE	2	Measurement done
Flash Subsystem	Flash Controller	3	Flash controller
	PFW		Program Flash Write
	PCACHE		Page Cache
PORT-A	PortA Input Change Interrupt	4	PortA input change interrupt
PORT-B	PortB Input Change Interrupt	5	PortB input change interrupt
PORT-C	PortC Input Change Interrupt	6	PortC input change interrupt
PORT-D	PortD Input Change Interrupt	7	PortD input change interrupt
PORT-E	PortE Input Change Interrupt	8	PortE input change interrupt
DMAC	SUSP 0..3	9	Channel suspend
	TCMPL 0..3		Transfer complete
	TERR 0..3		Transfer error
	SUSP 4..15	10	Channel suspend
	TCMPL 4..15		Transfer complete
	TERR 4..15		Transfer error
EVSYS	EVD 0..3	11	Event Detected Channel n interrupt
	OVR 0..3	11	Overrun Channel n interrupt
	EVD 4..11	12	Error
	OVR 4..11	12	Overrun Channel n interrupt
PAC	ERR	13	Error
RAMECC	SINGLEE-0	14	Single bit error
RAMECC	DUALE-1	14	Dual bit error
SERCOM0 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	15	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM1 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	16	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM2 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	17	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM3 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	18	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM4 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	19	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM5 Order: USART, I2CM, I2CS, SPI	DRE, MB, PERC, DRE	20	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
SERCOM6 Order: I2CM, I2CS	MB, PERC	21	Data Register Empty, Host on Bus, Stop Received
	TXC, SB, AMATCH, TXC		Transmit Complete, Device on Bus, Address Match
	RXC, -, DRDY, RXC		Receive Complete, Data Ready
	RXS, -, -, SSL		Receive Start, Device Select Low
	CTSIC, -, -, -		Clear to Send Input Change
	RXBRK, -, -, -		Receive Break
	ERR, ERR, ERR, ERR		Error
TCC0	CNT	22	Count
	DFS		Debug Fault State
	ERR		Capture Overflow Error
	FAULTA		Recoverable Fault A
	FAULTB		Recoverable Fault B
	FAULT0		Non-Recoverable Fault 0
	FAULT1		Non-Recoverable Fault 1
	OVF		Overflow/Underflow
	TRG		Retrigger event
	UFS		Non-Recoverable Update Fault
	MC		Match or Capture
TCC1	CNT	23	Count
	DFS		Debug Fault State
	ERR		Capture Overflow Error
	FAULTA		Recoverable Fault A
	FAULTB		Recoverable Fault B
	FAULT0		Non-Recoverable Fault 0
	FAULT1		Non-Recoverable Fault 1
	OVF		Overflow/Underflow
	TRG		Retrigger event
	UFS		Non-Recoverable Update Fault
	MC		Match or Capture
TCC2	CNT	24	Count
	DFS		Debug Fault State
	ERR		Capture Overflow Error
	FAULTA		Recoverable Fault A
	FAULTB		Recoverable Fault B
	FAULT0		Non-Recoverable Fault 0
	FAULT1		Non-Recoverable Fault 1
	OVF		Overflow/Underflow
	TRG		Retrigger event
	UFS		Non-Recoverable Update Fault
	MC		Match or Capture
TC0	OVF	25	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC1	OVF	26	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC2	OVF	27	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC3	OVF	28	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC4	OVF	29	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC5	OVF	30	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC6	OVF	31	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC7	OVF	32	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC8	OVF	33	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
TC9	OVF	34	Overflow/Underflow
	ERR		Error
	MC		Match or Capture
ADCTRL	GIRQ	35	Global
	DIRQ0		Digital comparator
	DIRQ1		Digital comparator
	AIRQ0		Digital filter
	AIRQ1		Digital filter
	FLT	36	Fault
	EOS_RDY	37	End-of-screen ready
	FCC	37	First class channel BVMI DMA group
	BGVR_RDY	38	RDY ADC analog circuit
AC	COMP0	39	Change in comparator0 status
	COMP1		Change in comparator1 status
	WIN_0		Change in window0 status
Crypto	INT0	40	Crypto Host
Crypto	INT1	41	TRNG
QSPI	LINE	42	QSPI
Wireless SIB	ZB_INT0	43	802.15.4 interrupt
	BT_INT0	44	Bluetooth interrupt
	BT_INT1	45	Bluetooth interrupt
	ARBITER	46	Arbiter
	CLKI_WAKEUP_NMI	47	Clock input with a wake-up trigger
CVD	CVD	48	CVD event
Crypto	INT2	49	Crypto interrupt2
QEI	upbs_event[1]	50	QEI interrupt
CAN0	LINE0	51	CAN 0 LINE0
	LINE1		CAN 0 LINE1
	ERROR		Error
CAN1	LINE0	52	CAN1 LINE0
	LINE1		CAN1 LINE1
	ERROR		Error
ETH	eth_intreq_q	53	Ethernet interrupt signal synchronous to APB clock
USB	usbcore1_interrupt	54	USB core 1 interrupt
Wireless SIB	pll_locked_out	55	PLL lock for Boot
Wireless SIB	pll_locked_out	56	PLL lock for User
BLE Stack⁽¹⁾	Firmware Interrupt only	57	Firmware interrupt only
Note: The last interrupt index is a software only interrupt intended to be used as a software interrupt by the Bluetooth LE stack. It will be used as BT_LC_IRQ by the stack. This does not have a associated hardware interrupt. “-” indicates that there is no source for that module.