26.10.6 Interrupt Flag Status and Clear in COUNT16 mode (CTRLA.MODE=1)
| Name: | INTFLAG |
| Offset: | 0x0C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| OVF | TAMPER | CMPn[5:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PER7 | PER6 | PER5 | PER4 | PER3 | PER2 | PER1 | PER0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – OVF Overflow
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.OVF is ‘1’ .
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Overflow interrupt flag.
Bit 14 – TAMPER TAMPER
This flag is set after a tamper condition occurs, and an interrupt request is generated if INTENCLR.TAMPER/ INTENSET.TAMPER is ‘1’ .
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Tamper interrupt flag.
Bits 13:8 – CMPn[5:0] Compare n [n = 5..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMPn is ‘1’ .
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare n interrupt flag.
Bits 12:8 – CMPn[4:0] Compare n [n = 4..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMPn is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare n interrupt flag.
Bits 8, 9, 10, 11 – CMPn Compare n [n = 3..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMPn is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare n interrupt flag.
Bits 10:8 – CMPn[2:0] Compare n [n = 2..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMPn is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare n interrupt flag.
Bits 8, 9 – CMPn Compare n [n = 1..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMPn is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare n interrupt flag.
Bit 8 – CMP0 Compare 0
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request is generated if INTENCLR/SET.COMP0 is ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Compare 0 interrupt flag.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PERn Periodic Interval n [n = 7..0]
This flag is cleared by writing a ‘1’ to the flag.
This flag is set on the 0-to-1 transition of prescaler bit [n+2], and an interrupt request is generated if INTENCLR/SET.PERx is one.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Periodic Interval n interrupt flag.