33.5.1 I/O Lines

Using the USART’s I/O lines requires the I/O pins to be configured using the System Configuration registers (See System Configuration and Register Locking (CFG) from Related Links.) (SCOM_HSEN[2:0] of CFGCON1/DEVCFG1 register). If SERCOM pins are selected through PPS, the PPS registers have to be configured. See I/O Ports and Peripheral Pin Select (PPS) from Related Links.

If SCOMx_HSEN = 1, SERCOM uses dedicated pins.

If SCOMx_HSEN = 0, SERCOM uses the PPS path and I/O pins are multiplexed to pin groups defined in the PPS section.

Note: Only SERCOM0/1/2 can be configured using either dedicated pins or PPS path.

When the SERCOM is used in the USART mode, the SERCOM controls the direction and value of the I/O pins according to the following table. If the receiver or transmitter is disabled, these pins can be used for other purposes.

Table 33-2. USART Pin Configuration
Pin	Pin Configuration
TxD	Output
RxD	Input
XCK	Output or input

The configuration of the Transmit Data Pinout and Receive Data Pinout bit fields in the Control A register (CTRLA.TXPO and CTRLA.RXPO, respectively) defines the physical position of the USART signals in the above table.