10.3.2 Configuration

Figure 10-1. High-Speed Bus Matrix Inter-connectivity
Table 10-5. High Speed Bus Matrix Initiator
High-Speed Bus Matrix InitiatorInitiator ID
CM4CPU - Cortex-M4 System Bus0
CM4CC - Cortex-M4 CMCC Bus1
DMA RD – DMA-Read2
DMA-WR – DMA-Write3

DSU/ICD (Test mode only) – Device Service Unit/In-Chip Debugger

4
CRYPTO5
ADC6
USB7
CAN08
CAN19
GMAC10
Table 10-6. High-Speed Bus Matrix Target
High-Speed Bus Matrix TargetTarget ID
SRAM1 – SRAM Port 10
SRAM2 – SRAM Port 21
SRAM3 – SRAM Port 32
SRAM4 – SRAM Port 43
PCHE – Prefetch Cache of CM4CC4
PCHE – Prefetch Cache of Peripherals5
PB-BRIDGE-A – Peripheral Bridge A6
PB-BRIDGE-B – Peripheral Bridge B7
PB-BRIDGE-C – Peripheral Bridge C8
PB-(PIC) – Peripheral Bridge D9
QSPI – Quad SPI Interface10
ROT – Root of Trust11
CRYPTO12
PB-BRIDGE-D – Peripheral Bridge D13