36.8.8 Interrupt Flag Status and Clear

Name: INTFLAG
Offset: 0x1C
Reset: 0x00000000
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
      INSTREND CSRISE 
Access R/WR/W 
Reset 00 
Bit 76543210 
     ERRORTXCDRERXC 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 10 – INSTREND Instruction End

This bit is set when an Instruction End was detected.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the flag.

Bit 8 – CSRISE Chip Select Rise

The bit is set when a Chip Select Rise was detected.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the flag.

Bit 3 – ERROR Overrun Error

This bit is set when an ERROR has occurred.

An ERROR occurs when RXDATA is loaded at least twice from the serializer.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit clears the flag.

Bit 2 – TXC Transmission Complete

ValueDescription
0As soon as data are written in TXDATA.
1TXDATA and internal shifter are empty. If a transfer delay was defined, TXC is set after the completion of such delay.

Bit 1 – DRE Transmit Data Register Empty

This bit is ‘0’ when the QSPI is disabled or at Reset.

The bit is set as soon as ENABLE bit is set.

ValueDescription
0Data were written to TXDATA and not yet transferred to the serializer.
1The last data written in the TXDATA were transferred to the serializer.

Bit 0 – RXC Receive Data Register Full

ValueDescription
0No data were received since the last read of RXDATA.
1Data were received and the received data were transferred from the serializer to RXDATA since the last read of RXDATA.