Microcontroller Subsystem (MSS)

  • Hard 50 MHz 32-Bit ARM® Cortex®-M3
    • Fully Tested Across Military Temperature Range 
(–55 °C to 125 °C)
    • 1.25 DMIPS/MHz Throughput from Zero Wait State Memory
    • Memory Protection Unit (MPU)
    • Single Cycle Multiplication, Hardware Divide
    • JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces
  • Internal Memory
    • Embedded Nonvolatile Flash Memory (eNVM), 128 KB to 512 KB
    • Embedded High-Speed SRAM (eSRAM), 16 KB to 64 KB, Implemented in 2 Physical Blocks to Enable Simultaneous Access from 2 Different Masters
  • Multi-Layer AHB Communications Matrix
    • Provides up to 16 Gbps of On-Chip Memory Bandwidth,1 Allowing Multi-Master Schemes
  • 10/100 Ethernet MAC with RMII Interface2
  • Programmable External Memory Controller, Which Supports:
    • Asynchronous Memories
    • NOR Flash, SRAM, and PSRAM
    • Synchronous SRAMs
  • Two I2C Peripherals
  • Two 16550 Compatible UARTs
  • Two SPI Peripherals
  • Two 32-Bit Timers
  • 32-Bit Watchdog Timer
  • 8-Channel DMA Controller to Offload the Cortex-M3 processor from Data Transactions
  • Clock Sources:
    • 32 kHz to 20 MHz Main Oscillator
    • Battery-Backed 32 KHz Low Power Oscillator with Real-Time Counter (RTC)
    • 100 MHz Embedded RC Oscillator; Up to 3% Accurate at Military Temperature
    • Embedded Analog PLL with 4 Output Phases (0, 90, 180, and 270)
1

Theoretical maximum

2

A2F500 devices