Low Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based
CMOS Process
Nonvolatile, Live at Power-Up, Retains Program When Powered
Off
350 MHz System Performance
Embedded SRAMs and FIFOs
Variable Aspect Ratio 4608-Bit SRAM Blocks
x1, x2, x4, x9, and x18 Organizations
True Dual-Port SRAM (excluding x18)
Programmable Embedded FIFO Control Logic
Secure ISP with 128-Bit AES via JTAG
FlashLock® to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2 Integrated
Analog PLLs
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
