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Military Grade SmartFusion Customizable System-on-Chip (cSoC)
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Product Benefits
Microcontroller Subsystem (MSS)
High-Performance FPGA
Programmable Analog
Analog Front-End (AFE)
Analog Compute Engine (ACE)
I/Os and Operating Voltage
SmartFusion cSoC Family Product Table
SmartFusion cSoC Device Status
SmartFusion cSoC Block Diagram
SmartFusion cSoC System Architecture
Product Ordering Codes
Temperature Grade Offerings
1
SmartFusion Family Overview
1.1
Introduction
1.2
General Description
2
SmartFusion DC and Switching Characteristics
2.1
General Specifications
2.2
Calculating Power Dissipation
2.3
User I/O Characteristics
2.4
VersaTile Characteristics
2.5
Global Resource Characteristics
2.6
RC Oscillator
2.7
Main and Lower Power Crystal Oscillator
2.8
Clock Conditioning Circuits
2.9
FPGA Fabric SRAM and FIFO Characteristics
2.10
Embedded Nonvolatile Memory Block (eNVM)
2.11
Embedded FlashROM (eFROM)
2.12
JTAG 1532 Characteristics
2.13
Programmable Analog Specifications
2.14
Serial Peripheral Interface (SPI) Characteristics
2.15
Inter-Integrated Circuit (I
2
C) Characteristics
3
SmartFusion Development Tools
3.1
Types of Design Tools
3.2
SmartFusion Ecosystem
3.3
Middleware
4
SmartFusion Programming
4.1
In-System Programming
4.2
In-Application Programming
4.3
Typical Programming and Erase Times
4.4
References
5
Pin Descriptions
5.1
Supply Pins
5.2
User-Defined Supply Pins
5.3
Global I/O Naming Conventions
5.4
User Pins
5.5
Special Function Pins
5.6
JTAG Pins
5.7
Microcontroller Subsystem (MSS)
5.8
Analog Front-End (AFE)
5.9
Analog Front-End Pin-Level Function Multiplexing
5.10
Pin Assignment Tables
6
Revision History
Microchip FPGA Support
Microchip Information
The Microchip Website
Product Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System
Worldwide Sales and Service
