3.2 Features List

The PL360MB board includes the following features:
  • PL360 PLC Transceiver:
    • Multi-protocol PLC modem:
      • G3-PLC, profiles CENELEC, FCC and ARIB
      • PRIME 1.3 and PRIME 1.4
    • 96 kB (up to 128 kB) of SRAM for program
    • 96 kB (down to 64 kB) of SRAM for data
    • One SPI peripheral to external MCU
    • Zero-Cross Detection
    • Embedded PLC Analog Front End (AFE)
    • Low power consumption in transmission and reception
    • Fuses burning circuit
  • SAM4CMS16C MCU:
    • Master Core:
      • ARM Cortex®-M4 running at up to 120MHz
      • Memory Protection Unit (MPU)
      • DSP instruction set
      • Thumb®-2 instruction set
      • Instruction and Data Cache Controller with 2 Kbytes cache memory
      • 1024 Kbytes of Flash, 128 Kbytes of SRAM, 8 Kbytes of ROM
    • Coprocessor:
      • ARM Cortex-M4F running at up to 120 MHz
      • IEEE® 754 compliant, single precision Floating-Point Unit (FPU)
      • DSP instruction set
      • 16 Kbytes of embedded SRAM (SRAM1)
      • 8 Kbytes of embedded SRAM (SRAM2)
      • Cryptography
  • Linear AC/DC 115/230 VAC 50/60 Hz Power Supply
  • Selectable 12/16 VDC Power Supply for PLC Power Amplifier
  • Back-Up Circuit with Battery
  • Mains Zero-Crossing Detector Circuit
  • Support to PLC Coupling Boards PLCOUPxxx
  • Metrology:
    • Single phase measurements for voltage (between a voltage range of 85V-264V) and current (between a current range of 2-200A) with external Rogowski coils sensor, current transformer and shunt resistor
    • PWM optical energy indication
    • PWM isolated energy indication
    • Optical UART1
    • Relays control port connector
  • Peripherals:
    • Liquid crystal display
    • Supply monitor
    • TWI 1Mbit EEPROM
    • CryptoAuthentication™ device
    • User LEDs
    • Force wake-up and tamper switch buttons
    • Reset button
    • Isolated UART0 over USB and non isolated UART0 & UART1 over CMOS levels
    • Xplained PRO target connector
    • JTAG debugging port
Figure 3-2. PL360MB Board Architecture