45 Revision History

Revision A (December 2025)

This is the initial version of the document.

Revision B (March 2026)

This revision incorporates the following updates:

  • Sections:
    • Updated High-Speed Analog-to-Digital Converters, Peripheral Features, Analog Features, Qualification, Integrated Touch Controller (ITC), 3.3.12.2.1. DSP Multiply Instructions, 3.4.3.7. TAG Memory Parity, 3.4.3.7.1. TAG Operation, 3.4.3.8.1. Cache Mode, 3.4.4.4. Module Operation When Cache Enabled, 3.4.4.4.1. ISB Buffers, 4.1.1.1. Unique Device Identifier (UDID), 4.5.1. Execute from RAM, 8.6. Cryptographic Accelerator Module (CAM), 8.6.1.4. Asymmetric Crypto Engine, 10.6.5. INTTREG, 10.8. Interrupt Sequence, 11.4.7. Virtual Output Pins, 11.4.9. I/O Multiplexing with Multiple Peripherals, 11.4.10. Change Notice (CN), 11.4.10.1. CN Configuration and Operation, 11.4.11. I/O Integrity Module (IOIM), 12.4.3.2. Primary Oscillator Pin Functionality, 12.4.4. Internal Fast RC (FRC) Oscillator, 12.4.5. BFRC Oscillator, 12.4.6. Phase-Locked Loop (PLL), 12.4.6.3.1. Setup for Using PLL with the Primary Oscillator (POSC), 15. High-Resolution PWM with Fine-Edge Placement, 15.5.2.2.4. LLC Resonant Converter Mode, 15.5.2.3.1. Complementary Output Mode, 16. 40 MSPS Analog-to-Digital Converter (ADC), 16.6.3. Windowed Multiple Conversions, 16.5.4. Integration of the Multiple Samples, 18.4.1. Excitation Signal Generation, 18.4.2.1. ADC Input Selection and Coherent Demodulation, 18.4.2.1.1. ADC Trigger Signals, 18.4.2.2. Excitation Signal Feedback Delay, 18.4.2.3. CIC Filter, 18.4.2.3.2. Heterodyne (Synchronous Demodulation), Operating Modes, Register Source Mode, External Signal Source Mode, 18.4.2.3.4. Auto Shift of Filter Output, 18.4.3. CORDIC Block, 18.4.3. CORDIC Block, 18.5. Interrupts, 20.2. Architectural Overview, 22. Serial Peripheral Interface (SPI), 24.4.5.1.2. Handling GETMXDS CCC, 24.4.5.1.4. Handling ENTDAA, GETPID and GETDCR, 27.6.1. Timer Operation in Sleep Mode and 45. Product Identification System.
    • Added 16-Bit Resolution Mode, 16-bit Conversion Example, 24. Improved Inter-Integrated Circuit (I3C), 10.6.5 Vector Fail Address, and 15.5.2.6.3 PCI Output Control Priority.
    • Removed 3.4.3.6.4. Implications of Variable NVM Wait States, 3.4.3.9.2. Stream Buffers, 3.4.4.13.2. Cache Coherency After a BOOTSWP Event and 17. Integrated Touch Controller (ITC).
    • Split 40 MSPS Analog-to-Digital Converter (ADC) and Integrated Touch Controller (ITC) into two separate sections.
  • Registers:
    • Updated 3.2.5 Core Mode Control Register, 3.2.6. Modulo Addressing Control Register, 3.2.8 X AGU Modulo Addressing End Register, 3.2.10 Y AGU Modulo Addressing End Register,3.2.15 Debug Hold PC Register , 3.4.2.5. Cache RAM Command Register (Address/Control), 6.2.1. Nonvolatile Memory (NVM) Control Register, 6.2.22. NVM CRC Seed Register, 7.1.11. FPED Configuration Register, 8.2.10. Peripheral Access Control Register 3, 8.6.2.1. Crypto Accelerator Enable Register, 9.1.1. Reset Control Register, 9.4.6.1. Voltage Monitor Control Register, 9.4.6.3 Voltage Monitor Fault Injection Configuration Register, 10.4.6. Interrupt Control and Status Register, 10.4.13. Interrupt Request Flags Register 4, 10.4.24. Interrupt Enable Register 4, 10.4.48. Interrupt Priority Register 18, 10.4.49. Interrupt Priority Register 19, 12.3.2. Oscillator Configuration Register, 12.3.5. Clock Generator Control Register, 12.3.6. Clock Generator Divider Register, 12.3.7. PLL Control Register, 12.3.8. PLL Divider Register, 15.4.1. PWM Clock Control Register, 15.4.3. Frequency Scaling Minimum Period Register, 15.4.4. Master Phase Register, 15.4.8. Combinational Trigger Register, 15.4.9. Combinatorial PWM Logic Control Register, 15.4.10. PWM Event Output Control Register y, 15.4.11. PWM Generator x Control Register, 15.4.13. PWM Generator x I/O Control 1 Register, 15.4.14. PWM Generator x I/O Control 2 Register, 15.4.15. PWM Generator x Event 1 Register, 15.4.16. PWM Generator x Event 2 Register, 15.4.17. PWM Generator x F1 PCI 1 Register, 15.4.18. PWM Generator x F1 PCI 2 Register, 15.4.19. PWM Generator x F2 PCI 1 Register, 15.4.20. PWM Generator x F2 PCI 2 Register, 15.4.23. PWM Generator x Period Register, 15.4.27. PWM Generator x Leading-Edge Blanking Register, 15.4.28. PWM Generator x Phase Register, 15.4.29. PWM Generator x Duty Cycle Register, 15.4.30. PWM Generator x Dead-Time Register, 15.4.32. PWM Generator x Trigger A Register, 15.4.33. PWM Generator x Trigger B Register, 15.4.35. PWM Generator x Trigger D Register, 15.4.36. PWM Generator x Trigger E Register, 15.4.37. PWM Generator x Trigger F Register, 18.3.1. RDC Control Register, 18.3.2. RDC ADC Selection Register, 18.3.3. RDC Status Register, 18.3.4. RDC Excitation Signal Control Register, 18.3.5. RDC Excitation Signal Delay Register, 18.3.8. RDC CORDIC Block Angle Input Register, 18.3.13. CIC Status Register, 18.3.16. CIC Control 2 Register, 18.3.11. CIC Control 1 Register, 18.3.12. CIC Length Register, 18.3.13. CIC Status Register, 18.3.15. CIC Filter Input Timeout Counter Register, 18.3.18. CIC Channel x Input Register, 18.3.19. CIC Channel x Output Register, 18.3.20. CIC Channel x Decimated Accumulator Value Register, 19.3.5. DACx Data Register, 20.3.1. QEI 1 Control Register, 20.3.2. QEI 1 I/O Control Register, 20.3.3. QEI 1 Status Register, 22.3.1. SPIx Control Register 1, 28.3.2. CCPx Control Register 2, 37.2.2. Peripheral Module Disable 1 Register and 37.2.5. Peripheral Module Disable 4 Register.
    • Added 10.4.27 Interrupt Enable Register 7, 13.3.15 DMA Channel x Pattern Register, PWM Generator x CL PCI 1 Register, PWM Generator x CL PCI 2 Register, PWM Generator x FF PCI 1 Register, PWM Generator x FF PCI 2 Register, 15.4.25. PWM Generator x SP PCI 1 Register, 15.4.26. PWM Generator x S PCI 2 Register, 16.3.57 ADC 2 Channel x Secondary Accumulator Register, Peripheral Pin Select Output Register 32, Peripheral Pin Select Output Register 33,Peripheral Pin Select Output Register 34 and Peripheral Pin Select Output Register 35.
    • Removed 12.3.10. Reset Control Register because it is already in the Resets section.
  • Tables:
    • Updated Table 1. dsPIC33AK256MPS306 Family Device Features, Table 2. 36-Pin VQFN Complete Pin Function Descriptions, Table 3. 48-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 4. 64-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 5. Pinout I/O Descriptions, Table 9-2. Code Execution Start Time for Various Device Resets, Table 11-13. Output Selection for Remappable Pins (RPn), Table 12-3. Clock Generator Clock Resources, Table 12-4. PLL Clock Sources, Table 12-5. Clock Monitor Clock Resources, Table 12-6. Primary Oscillator Modes, Table 12-7. Clock Pin Function Selection, Table 12-8. PLL Mode Defaults, Table 13-7. RELOADS/RELOADD/RELOADC Bits and Data Transfer Modes, Table 14-2. CLKSEL Clock Selection bit,Table 15-2. MCLKSEL PWM Master Clock Selection, Table 16-2. ADC Input Availability, Table 16-4. Output Format, Table 18-2. CIC Block Summary, Table 21-2. UART Clock (FUART) Source Selection bits, Table 22-2. SPI Host Clock Source Selection bit, Table 26-2. CLKSEL Selection bit, Table 27-2. TCS Timer Clock Source Select bit, Table 28-2. CLKSEL Time Base Clock Select bits, Table 29-4. DS3 Data Selection MUX 3 Signal Selection bits, Table 42-2. Operating MHz vs. Voltage, Table 42-4. Thermal Packaging Characteristics, Table 42-10. DC Characteristics: PWM Delta Current, Table 42-12. DC Characteristics: PLL Delta Current, Table 42-13. DC Characteristics: ADC Δ Current, Table 42-14. DC Characteristics: Comparator + DAC Delta Current, Table 42-15. Op Amp Delta Current, Table 42-16. I/O Pin Input Specifications, Table 42-17. I/O Pin Input Leakage Specifications, Table 42-20. Capacitive Loading on Output Pins, Table 42-21. External Clock Timing Requirements, Table 42-22. PLLn Timing Specifications, Table 42-23. Peripheral Input Clock Timing Specifications, Table 42-24. Internal FRC Accuracy, Table 42-25. I/O Timing Requirements, Table 42-38. I3C Push-Pull Timing Parameters for SDR and HDR-DDR, Table 42-39. UARTx Module I/O Timing Requirements, Table 42-40. ADC Module Specifications, Table 42-42. High-Speed Analog Comparator Module Specifications and Table 42-46. Operational Amplifier Specifications.
    • Added Table 42-47. UREF Module Specification and Table 42-48. RDC Module Specification.
  • Figures:
    • Updated Figure 1-1. dsPIC33AK256MPS306 Family Block Diagram, Figure 6-3. Boot Sequence Number, Figure 9-3. Window Comp, Figure 10-4. Interrupt Latency, Figure 12-1. Oscillator Module Block Diagram, Figure 12-4. Clock Generator, Figure 12-9. PLL Block Diagram, Figure 15-15. Override and SWAP Signal Flow, Complementary Mode, Figure 12-2. Clock Generator, Figure 18-9. CIC Channel Block Diagram and Figure 24-1. I3C Hardware Block Diagram.
  • Examples:
    • Updated Example 11-1. Configuring UART1 Input and Output Functions, Example 11-2. Virtual PPS Connection, Example 11-3. IOIM Code, Example 11-4, Example 12-2. Code Example for Using PLL with the Primary Oscillator (POSC), Example 13-5. Code for Fixed to Block Continuous Transfer (Peripheral to Memory), Example 13-6. Null Write Mode, Example 18-1. RDC Configuration Code, Example 25-5. Short PWM Code (SPC) Support and Example 25-6. SENT Reception (SPC Pulse Transmission).
    • Removed Example 6-4. Partition Swap due to redundancy.
    • Equations:
  • Updated 12-8. FVCO Calculation and Equation 12-9. FPLLO Calculation.

Minor grammatical corrections and formatting changes have been made throughout the document.

Revision C (July 2026)

This revision incorporates the following updates:

  • Sections:
    • Updated Operating Conditions, High-Speed Analog-to-Digital Converters, Controller Features, Security Features, Analog Features, Qualification, Vendor Specific Directed Read CCC’s, 3.3.18.3.1. Bit-Reversed Addressing Implementation, 3.6.3.2. Subnormal Number, 5.4.3.1. BIST at Start-up, 8. Security Module, 8.6.3. Operations, 8.6.3.3. Operations in Sleep/Idle Modes, 9.4.7.2. Device Reset Request, 11.4.6. Considerations for Peripheral Pin Selection, 13.4.7.1. Common Transfer Mode Sequence, 13.4.8.2. Fixed to Block, 13.5.1.2. Transfer Size, 13.5.2. Source Descriptor Table (SDT), 13.5.3. Destination Descriptor Table (DDT), 14.7.13. Transmit State Diagram, 15.2. High-Resolution Mode (Fine Edge Placement), 15.4.2. Frequency Scale Register, 15.4.7. Linear Feedback Shift Register, 15.4.10. PWM Event Output Control Register y, 15.4.12. PWM Generator x Status Register, 15.4.17. PWM Generator x F1 PCI 1 Register, 15.4.25. PWM Generator x SP PCI 1 Register, 16.4.1. Channels, 16.4.4. Conversions, 16.5. 16-bit Resolution Mode, 17.4.16. Acquisition Sequencer Commands, 17.4.18. Hardware Coded Sequences, 17.5.1. CVD Scan of Three Analog Inputs Using a Hardcoded Processing Sequence, 17.5.2. CVD Scan of All Analog Inputs Using a Custom Processing Sequence Defined in Software, 24.4.4.1. SCL Generation and Timings, 24.4.5.1.3. Handling the GETSTATUS CCC, 24.4.5.1.4. Handling ENTDAA, GETPID and GETDCR, Vendor Specific Write CCCs, Vendor Specific Directed Read CCC’s, 24.4.5.2.1. Handling Private Receive (Controller Write) Transfers, 24.4.5.2.2. Handling Private Transmit (Controller Read) Transfers, Target Interrupt Request Generation with Virtual Target, 24.4.5.3. Hot-Join Request, 24.4.5.4. Target Interrupt Request Generation, 24.4.5.5. Controller Request Generation, Detecting Dead Bus, Recovery Sequence and 24.4.5.6.2. Extended Response Data Structure, 25.4.2.2. Receiver Status, 26.5.4. Broadcast Command Code Example, 27.4.2. Synchronous External Clock Counter Mode, 27.4.3. Gated Timer Mode, 27.4.3.2. Gated Timer Initialization Steps, 27.4.7. Asynchronous External Clock Counter Initialization Steps, 27.4.8. Timer Prescalers, 27.4.9. Writing to TxCON, TMRx and PRx Registers and 28.4.4.4.6. Output Polarity Control.
    • Added High-Temperature Electrical Characteristics.
  • Registers:
    • Updated 3.2.13. Force Execution Instruction Register 1, 3.2.14. Force Execution Instruction Register 2, 3.2.16. Vector Fail Address Register, 3.4.2.3. Cache Fault Injection Register, 3.4.2.5. Cache RAM Command Register (Address/Control), 3.4.2.6. Tag Data Register, 3.4.4.5.1. Buffer Slice Architecture, 3.5.2.2. HPCSEL0 Register, 3.5.2.3. HPCSEL1 Register, 6.2.1. Nonvolatile Memory (NVM) Control Register, 6.2.11. NVM ECC Fault Injection Address Register, 6.2.12. NVM ECC Error Address Register, 6.2.14. NVM ECC Error Data 1 Register, 6.2.19. NVM CRC Control Register, 6.2.20. NVM CRC Start Address Register, 6.2.21. NVM CRC End Address Register, 6.3.3. Error Correcting Code (ECC), 6.4.3.4.1. Inactive Panel Erase Sequence, 7.1.2. FICD Configuration Register, 7.1.3. FDEVOPT Configuration Register, 7.1.4. FWDT Configuration Register, 7.1.6. FPRxCTRL Configuration Register, 7.1.7. FPRxST Configuration Register, 7.1.13. FWPUCB Configuration Register, 7.2.2. Device ID Register, 8.2.5. Protection Region n Start Address Offset Register, 8.2.9. Peripheral Access Control Register 2, 8.6.2.1. Crypto Accelerator Enable Register, 9.1.1. Reset Control Register, 10.4.1. Interrupt Control Register 1, 10.4.3. Interrupt Control Register 3, 10.4.4. Interrupt Control Register 4, 10.4.7. Interrupt Vector Base Address Register, 10.4.9. Interrupt Request Flags Register 0, 10.4.10. Interrupt Request Flags Register 1, 10.4.11. Interrupt Request Flags Register 2, 10.4.12. Interrupt Request Flags Register 3, 10.4.13. Interrupt Request Flags Register 4, 10.4.14. Interrupt Request Flags Register 5, 10.4.15. Interrupt Request Flags Register 6, 10.4.16. Interrupt Request Flags Register 7, 10.4.17. Interrupt Request Flags Register 8, 10.4.18. Interrupt Request Flags Register 10, 10.4.19. Interrupt Request Flags Register 11, 10.4.20. Interrupt Enable Register 0, 10.4.21. Interrupt Enable Register 1, 10.4.22. Interrupt Enable Register 2, 10.4.23. Interrupt Enable Register 3, 10.4.24. Interrupt Enable Register 4, 10.4.30. Interrupt Enable Register 11, 10.4.31. Interrupt Priority Register 0, 10.4.37. Interrupt Priority Register 6, 10.4.39. Interrupt Priority Register 8, 10.4.41. Interrupt Priority Register 10, 10.4.42. Interrupt Priority Register 11, 10.4.50. Interrupt Priority Register 20, 10.4.57. Interrupt Priority Register 27, 10.4.64. Interrupt Priority Register 45, 10.4.65. Interrupt Priority Register 46, 10.4.65. Interrupt Priority Register 46, 11.3.1. Input Data Register, 11.3.5. Interrupt Change Notification Flag for Register, 11.3.6. Analog Select Register, 11.3.21. Peripheral Pin Select Input Register 9, 11.3.37. Peripheral Pin Select Input Register 28, 11.3.55. IOIM x Control Register, 11.3.56. IOIM x Status Register, 12.3.3. Reference Clock Fail Status Register, 12.3.5. Clock Generator Control Register, 12.3.6. Clock Generator Divider Register, 12.3.7. PLL Control Register, 12.3.8. PLL Divider Register, 12.3.10. User Clock Diagnostics Control Register, 12.3.12. Clock Monitor Control Register, 12.3.22. BFRC Controller Register, 13.3.7. DMA Channel x Interrupt Register, 14.4.1. CAN FD 1 Control Register, 14.4.8. CAN Interrupt Register, 14.4.13. CAN Transmit Request Register, 14.4.14. CAN Transmit/Receive Error Count Register, 14.4.15. CAN Bus Diagnostics Register 0, 14.4.16. CAN Bus Diagnostics Register 1, 14.4.17. CAN Transmit Event FIFO Control Register, 14.4.18. CAN Transmit Event FIFO Status Register, 14.4.21. CAN Transmit Queue Control Register, 15.4.1. PWM Clock Control Register, 15.4.2. Frequency Scale Register, 15.4.19. PWM Generator x F2 PCI 1 Register, 15.4.21. PWM Generator x CL PCI 1 Register, 15.4.23. PWM Generator x FF PCI 1 Register, 15.4.24. PWM Generator x FF PCI 2 Register, 15.4.30. PWM Generator x Duty Cycle Adjustment Register, 15.4.39. PWM Generator x Capture Register, 16.3.1. ADC n Control Register, 16.3.3. ADC n Data Ready Flags Register, 16.3.4. ADC n Result Ready Status Register, 16.3.5. ADC n Comparators Status Register, 16.3.7. ADC n Channel 0 Control Register 1, 16.3.8. ADC n Channel 0 Control Register 2, 16.3.15. ADC n Channel 1 Control Register 1, 16.3.16. ADC n Channel 1 Control Register 2, 16.3.17. ADC n Channel 2 Control Register 2, 16.3.18. ADC n Channel 2 Control Register 1, 16.3.19. ADC n Channel 3 Control Register 1, 16.3.20. ADC n Channel 3 Control Register 2, 16.3.21. ADC n Channel 4 Control Register 1, 16.3.22. ADC n Channel 4 Control Register 2, 16.3.23. ADC n Channel 5 Control Register 1, 16.3.24. ADC n Channel 5 Control Register 2, 16.3.25. ADC n Channel 6 Control Register 1, 16.3.26. ADC n Channel 6 Control Register 2, 16.3.33. ADC n Channel 7 Control Register 1, 16.3.34. ADC n Channel 7 Control Register 2, 16.3.41. ADC 3 Channel x Control Register 1, 16.3.42. ADC 3 Channel x Control Register 2, 17.3.1. Control Register 1, 17.3.3. ITC Status Register, 17.3.7. ITC Comparator Hit Register, 17.3.8. List x Control Register, 17.3.15. Records Pair Configuration Register, 17.3.16. Record x Result Register, 18.3.3. RDC Status Register, 18.3.14. CIC Invalid Input Sample Detection Control Register, 18.3.15. CIC Filter Input Timeout Counter Register, 19.3.3. DAC Control Register, 19.3.4. DACx Control Low Register, 20.3.2. QEI I/O 1 Control Register, 20.3.7. Velocity Counter 1 Hold Register, 21.3.4. UARTx Receive Buffer Register, 21.3.6. UARTx Timing Parameter A Register, 22.3.3. SPIx Status Register, 22.3.4. SPI Buffer Register, 22.3.5. SPIx Baud Rate Generator Register, 23.4.1. I2Cx Control Register, 23.4.2. I2Cx Control Register, 23.4.8. I2Cx Receive Data Register, 23.4.13. I2Cx Bus Time-out Selection Register, 23.4.18. I2C Host Input Delay Compensation Register, 24.3.1. Device Control Register, 24.3.3. Hardware Capability Register, 24.3.11. Reset Control Register, 24.3.12. Target Mode Event Status Register, 24.3.13. Interrupt Status Register, 24.3.18. Data Buffer Status Level Register, 24.3.20. Target Mode Device Operating Status Register (Target mode only), 24.3.22. Controller Mode Device Characteristics Table Pointer Register, 24.3.26. Target Mode Characteristic Register, 24.3.27. Target Mode Max Write/Read Length Register, 24.3.30. Target Mode Interrupt Request Register, 24.3.31. Target Interrupt Request Data Register, 24.3.32. Target IBI Response Register, 24.3.51. Target Mode Extended command Register's Transmit Buffer Threshold Status, 24.3.72. Secondary Controller Device Characteristic Table Location of Device(n) Register, 24.3.76. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.78. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.80. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.82. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.84. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.86. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.88. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.90. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.91. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.93. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.95. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.97. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.99. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.101. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.103. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.105. Secondary Commander Device Characteristic Table Location of Device(n) Register, 24.3.179. Virtual Target 1 Address Register, 24.3.182. I3C Target Characteristic Register for Virtual Target 1 Register, 24.3.183. Virtual Target 2 Address Register, 24.3.185. Provisional ID Register for Virtual Target 2, 24.3.186. I3C Target Characteristic Register for Virtual Target 2, 24.3.187. Virtual Target 3 Address Register, 24.3.189. Provisional ID Register for Virtual Target 3, 24.3.190. I3C Target Characteristic Register for Virtual Target 3, 24.3.191. Virtual Target 4 Address Register, 23.4.1. I2Cx Control Register, 23.4.8. I2Cx Receive Data Register, 24.3.193. Provisional ID Register for Virtual Target 4, 24.3.194. I3C Target Characteristic Register for Virtual Target 4, 24.3.195. I3C Control Register, 26.3.12. BiSS Configuration Register, 28.3.4. CCPx Status Register, 29.3.1. Configurable Logic Cell x Control Register, 31.2.1. CRC Control Register, 31.2.2. CRC XOR Register, 31.2.3. CRC Data Register, 33.2. UREF Control Register 1, 36.2.5. Deadman Timer Count Register, 37.2.1. Reset Control Register, 37.2.2. Peripheral Module Disable 1 Register, 37.2.3. Peripheral Module Disable 2 Register, 37.2.4. Peripheral Module Disable 3 Register and 37.2.5. Peripheral Module Disable 4 Register.
    • Updated all ADC registers to properly show 3 ADC instances and 12 ADC channels.
  • Tables:
    • Updated Table 1. dsPIC33AK256MPS306 Family Device Features, Table 4. 64-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 5. Pinout I/O Descriptions, Table 3-19. FP Instruction Exception Conditions, Table 4-1. UDID Address, Table 5-1. Data Memory, Table 6-1. Device Memory Attributes, Table 9-1. Reset Flag Bit Operation, Table 9-4. Status Bits, Their Significance and the Initialization Condition for RCON Register, Table 10-1. Interrupt Vector DetailsTable 11-2. PORTB Availability, Table 11-4. PORTD Availability, Table 11-5. ANSELA Availability, Table 11-10. Selectable Input Sources (Maps Input to Function), Table 11-11. Pin Correlation to Input Remap #, Table 11-13. Output Selection for Remappable Pins (RPn), Table 11-17. IOIM Test Conditions, Table 12-3. Clock Generator Clock Resources, Table 12-4. PLL Clock Sources, Table 12-5. Clock Monitor Clock Resources, Table 13-7. RELOADS/RELOADD/RELOADC Bits and Data Transfer Modes, Table 13-15. Descriptor-Based Operational Sequence, Table 15-1. PWM Summary Table, Table 16-2. ADC Input Availability, Table 16-3. TRGnSRC Trigger Source Selection Bits Value Description, Table 20-4. PIMOD Supports in Varies Mode, Table 22-1. SPI Summary Table, Table 22-7. Sample SCKx Frequencies, Table 24-17. Supported CCC Transfers, Table 24-23. CRHDLY Byte Format, Table 24-27. Extended Transmit Command Data Structure, Table 24-30. Extended Transmit Command Data Structure, 28.4.3.1.2. Timer Clock Source Selection, Table 42-2. Operating MHz vs. Voltage, Table 24-3. Transfer Command Data Structure, Table 25-1. SENT Summary Table, Table 29-4. DS3 Data Selection MUX 3 Signal Selection bits, Table 30-3. PTG Output Descriptions, Table 42-12. DC Characteristics: PLL Delta Current, Table 42-15. Op Amp Delta Current, Table 42-18. I/O Pin Input Injection Current Specifications, Table 42-25. Internal FRC Accuracy, Table 42-27. Reset and Watchdog Timer Timing Requirements, Table 42-31. SPIx Host Mode (Half-Duplex, Transmit Only) Timing Requirements, Table 42-34. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Requirements, Table 42-36. I2Cx Bus Data Timing Requirements (Host Mode), Table 42-40. ADC Module Specifications, Table 42-41. ADC Module Specifications, Table 42-42. Die Temperature Diode Specifications, Table 42-45. DACx Output (DACOUTx Pins) Specifications, Table 42-47. Operational Amplifier Specifications, Table 43-2. Operating MHz vs. Voltage, Table 43-4. DC Characteristics: Operating Current (IDD) and Table 43-5. Idle Current (IIDLE).
    • Added Table 42-18. I/O Pin Input Injection Current Specifications.
    • Removed Table 14-2. CLKSEL Clock Selection bit.
  • Figures:
    • Updated Figure 11-5. IOIM Block Diagram, Figure 14-14. Message Memory Organization, Figure 14-48. Interrupt Multiplexing, Figure 24-10. Programming Flow to Switch from Controller to Target Mode, Figure 24-36. Vendor Specific Transmit Transfer, Figure 24-41. Flow Diagram for Target Interrupt Request (SIR) Generation and Figure 27-1. Timer Block Diagram.
  • Examples:
    • Updated Example 6-3. CRC Checksum Calculation, Example 11-1. Configuring UART1 Input and Output Functions, Example 11-2. Virtual PPS connection, Example 12-2. Code Example for Using PLL with the Primary Oscillator (POSC), Example 12-3. Code Example for Using PLL with 8 MHz Internal FRC, ,, Example 12-4. Frequency Measurement Function, Example 13-5. Code for Fixed to Block Continuous Transfer (Peripheral to Memory), Example 13-6. Null Write Mode and Example 14-3. Message Reception Code, Example 17-1. ADC 3 Initialization and ITC Enable Code, Example 24-2. Target Mode: After Dynamic Address is assigned, Perform Private Read and Write, Example 28-2. Setup for Dual Edge Buffered Compare Mode, Example 30-2. PTGCTRL Options, Example 31-2. Calculating the Non-Direct Initial Value (MOD bit = 0), Example 31-3. Routine to Get the Final CRC Result in Legacy Mode (MOD bit = 0), Example 31-4. CRC-SMBus (8-Bit Polynomial with 32-Bit Data, Big-Endian, MOD bit = 1), Example 31-5. CRC-16 (16-Bit Data with 16-Bit Polynomial, Little-Endian, MOD bit = 1), Example 31-6. CRC-32 (32-Bit Polynomial with 32-Bit Data, Little-Endian, MOD bit = 1) and Example 31-7. Data Width Switching (32-Bit Polynomial, Little-Endian, MOD bit = 1).
  • Equations:
    • Updated Equation 18-5. and Equation 32-3. VSHIFT Calculations.