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High-Performance Secure MCUs for Industrial IoT and Metering Applications, Up to 2MB Flash, 512K Dual-Port SRAM, Advanced Crypto and Security Features
High-Performance Secure MCUs for Industrial IoT and Metering Applications, Up to 2MB Flash, 512K Dual-Port SRAM, Advanced Crypto and Security Features
Product Pages
PIC32CX1025MTG PIC32CX2051MTG PIC32CX5112MTG
  1. Home
  2. 21 Parallel Input/Output Controller (PIO)
  3. 21.5 Functional Description
  4. 21.5.15 I/O Line Configuration Freeze
  5. 21.5.15.2 Software Freeze
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  • Description
  • Features
  • 1 Block Diagram
  • 2 Configuration Summary
  • 3 Package and Pinout
  • 4 Power Supply and Power Control
  • 5 Input/Output Lines
  • 6 Core and Interconnect
  • 7 Product Mapping and Peripheral Access
  • 8 Memories
  • 9 Safety and Security Features
  • 10 Real-Time Event Management
  • 11 Peripherals
  • 12 Cortex-M4 Processor (Arm)
  • 13 Flash Programming, Debug and Test Features
  • 14 ROM Code and Boot Strategies
  • 15 Supply Controller (SUPC)
  • 16 Reset Controller (RSTC)
  • 17 System Controller Write Protection (SYSCWP)
  • 18 Dual Watchdog Timer (DWDT)
  • 19 Clock Generator
  • 20 Power Management Controller (PMC)
  • 21 Parallel Input/Output Controller (PIO)
    • 21.1 Description
    • 21.2 Embedded Characteristics
    • 21.3 Block Diagram
    • 21.4 Product Dependencies
    • 21.5 Functional Description
      • 21.5.1 I/O Line Configuration Method
      • 21.5.2 Pull-Up and Pull-Down Resistor Control
      • 21.5.3 General Purpose or Peripheral Function Selection
      • 21.5.4 Output Control
      • 21.5.5 Synchronous Data Output
      • 21.5.6 Open-Drain Mode
      • 21.5.7 Output Line Timings
      • 21.5.8 Inputs
      • 21.5.9 Input Glitch and Debouncing Filters
      • 21.5.10 Input Edge/Level Interrupt
      • 21.5.11 Interrupt Management
      • 21.5.12 I/O Lines Lock
      • 21.5.13 Programmable Schmitt Trigger
      • 21.5.14 Programmable Slew Rate
      • 21.5.15 I/O Line Configuration Freeze
        • 21.5.15.1 Introduction
        • 21.5.15.2 Software Freeze
          • 21.5.15.2.1 Physical Freeze
          • 21.5.15.2.2 Interrupt Freeze
      • 21.5.16 Register Write Protection
    • 21.6 I/O Lines Programming Example
    • 21.7 Register Summary
  • 22 Real-Time Clock (RTC)
  • 23 Real-time Timer (RTT)
  • 24 General Purpose Backup Registers (GPBR)
  • 25 Special Function Registers (SFR)
  • 26 Special Function Registers Backup (SFRBU)
  • 27 Bus Matrix (MATRIX)
  • 28 Chip Identifier (CHIPID)
  • 29 Secure Embedded Flash Controller (SEFC)
  • 30 Memory to Memory (MEM2MEM)
  • 31 Peripheral DMA Controller (PDC)
  • 32 Cortex-M Cache Controller (CMCC)
  • 33 Flexible Serial Communication Controller (FLEXCOM)
  • 34 Quad Serial Peripheral Interface (QSPI)
  • 35 Segment LCD Controller (SLCDC)
  • 36 Timer Counter (TC)
  • 37 Analog-to-Digital Converter (ADC) Controller
  • 38 Analog Comparator Controller (ACC)
  • 39 Advanced Encryption Standard (AES)
  • 40 Advanced Encryption Standard Bridge (AESB)
  • 41 Secure Hash Algorithm (SHA)
  • 42 True Random Number Generator (TRNG)
  • 43 Integrity Check Monitor (ICM)
  • 44 Classical Public Key Cryptography Controller (CPKCC)
  • 45 Multi Channel Serial Peripheral Interface (MCSPI)
  • 46 Pulse Width Modulation Controller (PWM)
  • 47 Universal Asynchronous Receiver Transmitter (UART)
  • 48 Electrical Characteristics
  • 49 Mechanical Characteristics
  • 50 Marking
  • 51 Ordering Information
  • 52 Revision History
  • 53 Product Identification System
  • Microchip Information

21.5.15.2 Software Freeze

Once the I/O line configuration is done, it can be frozen by using the PIO I/O Freeze Configuration Register (PIO_IOFRx) of the corresponding group if the corresponding line is configured in User-Access mode or the PIO Privilege I/O Freeze Configuration Register (PIO_P_IOFRx) for Privileged-Access mode I/O lines.

DS60001780C

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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