Introduction

A Software-Defined Radio (SDR) is a communication system that utilizes a programmable medium to implement radio components like mixers, filters, modulators/demodulators, and detection circuits. This approach offers enhanced flexibility and capabilities in the system.

A well-designed Software-Defined Radio (SDR) typically comprises various fixed components, such as an antenna, front-end RF hardware, and an ADC or DAC. The remaining functionalities are implemented in a programmable medium, referred to as "soft" components. While general-purpose processors are commonly used for this purpose, they often lack the required I/O bandwidth and processing capabilities, except for the most basic SDR architectures. FPGA systems fulfill the demands of complex SDR implementations by offering both the necessary I/O bandwidth and processing capabilities.

This demonstration outlines an SDR application on the PolarFire® FPGA. Baseband processing is implemented on the FPGA and transmitted using a wideband RF transceiver, AD9371. The transceiver is configured via a soft Mi-V processor on the PolarFire FPGA.

This design demonstrates the following features:
  • Supports Wireless transmission of text or image files between two hardware setups
  • Supports the UART GUI to transmit and receive the data
  • Supports configuration of the AD9371 RF board using the Mi-V soft processor on FPGA device
  • Provides carrier frequency and phase offset correction using Costas loop
  • Supports FEC encoding to correct data transmission errors
  • Supports Symbol Timing Synchronization
  • Supports Custom Packetization and Depacketization Method
  • Supports configurable parameters for wide range blocks

The demo includes a user-friendly SDR Graphical User Interface (GUI) to configure transmit and receive data.

The Microchip PolarFire FPGA Evaluation Kit (MPF300-EVAL-KIT), which is RoHS-compliant, enables you to evaluate the PolarFire family of FPGAs with support for the following interfaces:

  • PCI Express Gen1 and Gen2
  • 1 GbE
  • DDR3 and DDR4 memory
  • FMC HPC with eight transceiver lanes
  • One full-duplex Transceiver SMAs
  • SFP+ Cage
  • UART interface to FTDI device
  • SPI interface to SPI Flash device

For more information about the PolarFire Evaluation kit, see PolarFire FPGA Evaluation Kit.