Digital Peripherals

• One Configurable Logic Block (CLB)
  • Interconnected fabric containing 32 Basic Logic Elements (BLE)
    • Each BLE contains one 16-input Look-Up Table (LUT) and one flip-flop
    • Schematically programmable using MPLAB Code Configurator
  • Dedicated 3-bit hardware counter
• Two Capture/Compare/PWM (CCP) Modules:
  • 16-bit resolution for Capture/Compare modes
  • 10-bit resolution for PWM mode
• Two Pulse-Width Modulators (PWM):
  • 10-bit resolution
• Four Configurable Logic Cells (CLC):
  • Integrated combinational and sequential logic
• One Configurable 8/16-Bit Timer (TMR0)
• One 16-Bit Timer (TMR1) with Gate Control
• One 8-Bit Timer (TMR2) with Hardware Limit Timer (HLT)
• Programmable CRC with Memory Scan:
  • Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
  • Calculate 32-bit CRC over any portion of Program Flash Memory
• One Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):
  • RS-232, RS-485, LIN compatible
  • Auto-wake-up on Start
• One Host Synchronous Serial Port (MSSP):
  • Serial Peripheral Interface (SPI) mode
    • Chip Select Synchronization
  • Inter-Integrated Circuit (I²C) mode
    • 7/10-bit Addressing modes
    • SMBus support
• Peripheral Pin Select (PPS):
  • Enables pin mapping of digital I/O
• Device I/O Port Features:
  • Up to 17 I/O pins
  • Individual I/O direction, open-drain, input threshold, slew rate and weak pull-up control
  • Interrupt-on-Change (IOC) on all pins
  • One external interrupt pin