Core Features

C Compiler Optimized RISC Architecture
Operating Speed:
- DC-32 MHz clock input
- 125 ns minimum instruction time
16-Level Deep Hardware Stack
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power Brown-out Reset (LPBOR)
Windowed Watchdog Timer (WWDT)

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