Introduction

This datasheet covers Antifuse family of FPGAs and Axcelerator devices, which provides exceptional design security and outstanding performance at densities of up to two million equivalent system gates. Axcelerator devices, which use our AX architecture, have a number of system-level capabilities including segmentable clocks, PLLs, chip-wide highway routing, embedded SRAM (with embedded FIFO control logic), and the capacity to carry logic. Axcelerator devices, which are developed using a CMOS antifuse process technique based on 0.15 µm and seven layers of metal, provide a higher level of performance that was previously limited to ASIC technology.