4 Revision History

The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.

Table 4-1. Revision History
Revision	Date	Description
A	10/2024	The following is the list of changes in revision A of the document: Migrated this document into Microchip template and updated the Microsemi links with Microchip links. Updated document number to DS50003755A from 5172160. Device AX125 has been discontinued in Table 3-1, Table 5-2, Table 6-3, and Table 7-4. Package FG676 and CQ352 has been discontinued for device AX500 Table 3-1, Table 5-2, and Table 7-4. Package FG896 and CG624 has been discontinued for device AX1000 Table 3-1, Table 5-2, and Table 7-4. Package FG1152 has been discontinued for device AX2000 Table 3-1, Table 5-2, and Table 7-4. In Table 2-2, under Parameter Range, Ambient temperature is changed to Junction temperature. In Package Pin Assignments, for AX2000 device in CG624 package pin, E8 function has been updated from GND to GND/LP.
18	03/2012	The following is the list of changes in revision 18 of the document: Updated Table 2-1 to correct the maximum DC core supply voltage (VCCA) from 1.6 V to 1.7 V (SAR 36786). The maximum input voltage (VI) was corrected from 3.75 V to 4.1 V (SAR 35419). Added values for tristate leakage current IOZ, and IIH and IIL in table Table 2-3 (SARs 35774, 32021). Figure 2-2 was updated to correct the units for the resistance from "W" to Ω (SAR 36415). In User I/Os ² section, the following sentence was added to clarify the slew rate setting (SAR 34943): The slew rate setting is effective for both rising and falling edges. Figure 2-3 was revised to show the VCCI and GND clamp diodes. The explanatory text above the figure was revised as well (SAR 34942). Equation for 5 V tolerance was corrected to change Vdiode from 0.6 V to 0.7 V (SAR 36786). Additional information was added to the Using the Weak Pull-Up and Pull-Down Circuits section to clarify how the weak pull-up and pull-down resistors are physically implemented (SAR 34945). The description for the CINCLK parameter in Table 2-23 was changed from "Input capacitance on clock pin" to "Input capacitance on HCLK and RCLK pin" (SAR 34944). Table 2-24 is new (SAR 34942). The minimum VIL for 1.5 V LVCMOS and PCI was corrected from –0.5 to –0.3 in Table 2-34 and Table 2-37 (SAR 34358). Support for simulating the GCLR/ GPSET feature in the Axcelerator Family was added in Libero software v9.0 SPI1. Reference to the section explaining this in the Antifuse Macro Library Guide was added to the R-Cell (SAR 26413). The enable signal in Figure 2-33 was corrected to show it is active low rather than active high (SAR 34946).
17	09/2011	The following is the list of changes in revision 17 of the document: The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The Axcelerator Family Device Status table indicates the status for each device in the device family. The Features section, Programmable Interconnect Element section, and Security section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 32865). The C180 package was removed from product tables and the Package Pin Assignments section (PDN 0909). Package names used in the Table 3-1 and Package Pin Assignments section were revised to match standards given in Package Mechanical Drawings (SAR 27395). The section User I/Os ² was updated as follows: "The user does not need to assign VREF pins for OUTBUF and TRIBUF. VREF pins are needed only for input and bidirectional I/Os" (SARs 24181, 24309). Power values in Table 2-4 were updated to reflect those of SmartPower (SAR 33945). Two parameter names were corrected in Figure 2-10. One occurrence of tENLZ was changed to tENZL and one occurrence of tENHZ was changed to tENZH (SAR 33890). The Timing Model section was updated with new timing values. Timing tables in the I/O Specifications section were updated to include enable paths. Values in the timing tables in the Voltage-Referenced I/O Standards section and Differential Standards section were updated. Table 2-67 was updated (SAR 33945). Figure 2-11 was replaced (SAR 33043). The timing tables for RAM and FIFO were updated (SAR 33945). "Data Registers (DRs)" values were modified for IDCODE and USERCODE (Data Registers (DRs) SARs 18257, 26406). The package diagram for the CQ208 package was incorrect and has been replaced with the correct diagram (SARs 23865, 26345).
16	10/2010	The following is the list of changes in revision 16 of the document: The datasheet was updated to include AX2000-CQ2526 information. MIL-STD-883 Class B is no longer supported by Axcelerator FPGAs and as a result was removed. A footnote was added to the Axcelerator Clock Management System section.
15	11/2008	The following is the list of changes in revision 15 of the document: RoHS-compliant information was added to the Ordering Information. ACTgen was changed to SmartGen because ACTgen is obsolete.
14	—	The following is the list of changes in revision 14 of the document: In Table 2-4, the units for the PLOAD, P10, and PI/O were updated from mW/MHz to mW/MHz. In the Pin Descriptions section, the HCLK and CLK descriptions were updated to include tie-off information. The Global Resource Distribution section was updated. The CG624 table was updated.
13	—	The following is the list of changes in revision 13 of the document: A note was added to Table 2-2. In the Package Thermal Characteristics, the temperature was changed from 150°C to 125°C.
12	—	The following is the list of changes in revision 12 of the document: Revised Ordering Information and timing data to reflect phase out of –3 speed grade options. Table 2-3 was updated.
11	—	The following is the list of changes in revision 11 of the document: The Packaging Data section is new. Table 2-2 was updated. Table 2-8 was updated. Table 2-11 was updated. The User I/Os ² was updated.
10	—	The following is the list of changes in revision 10 of the document: Figure 1-3 was updated. Table 2-2 was updated. The Power-Up/Down Sequence section was updated. Table 2-4 was updated. Table 2-5 was updated. The Timing Characteristics section was added. Table 2-7 was updated. Figure 2-1 was updated. The External Setup and Clock-to-Out (Pad-to-Pad) equations in the Hardwired Clock—Using LVTTL 24 mA High Slew Clock I/O section were updated. The External Setup and Clock-to-Out (Pad-to-Pad) in the Routed Clock—Using LVTTL 24 mA High Slew Clock I/O section were updated. The Global Pins section was updated. The User I/Os ² section was updated. Table 2-22 was updated. Figure 2-8 was updated. Figure 2-13 and Figure 2-14 were updated. The following timing parameters were renamed in I/O timing characteristic tables from Table 2-27 to Table 2-64: tIOCLKQ > tICLKQ tIOCLKY > tOCLKQ Timing numbers were updated from Table 2-27 to Table 2-82. The R-Cell section was updated. Figure 2-60 was updated. Figure 2-61 was updated. Figure Figure 2-68 was updated. Figure 2-69 was updated. Table 2-93 to Table 2-97 were updated. Table 2-102 to Table 2-106 were updated. The TRST section was updated. The Global Set Fuse section was added. A footnote was added to FG896 for the AX2000 regarding pins AB1, AE2, G1, and K2. Pinouts for the AX250, AX500, and AX1000 were added for CQ352. Pinout for the AX1000 was added for CG624.
9.0	—	The following is the list of changes in revision 9.0 of the document: Table 2-83 was updated. The Low Power Mode section was updated.
8.0	—	The following is the list of changes in revision 8.0 of the document: Table 3-1 has been updated. The Ordering Information section has been updated. The Device Resources section has been updated. The Temperature Grade Offerings section is new. The Speed Grade and Temperature Grade Matrix section has been updated. Table 2-14 has been updated. Table Table 2-15 has been updated. Table 2-1 has been updated. Table 2-2 has been updated. Table 2-3 has been updated. Table 2-4 has been updated. Table 2-5 has been updated. The Power Estimation Example section has been updated. The Thermal Characteristics section has been updated. The Package Thermal Characteristics section has been updated. The Timing Characteristics section has been updated. The Pin Descriptions section has been updated. Timing numbers have been updated from the 3.3V LVTTL section to the Timing Characteristics section. Many AC Loads were updated as well. Timing characteristics for the Hardwired Clocks and Routed Clocks sections were updated. Table 2-93 to Table 2-96 and Table 2-102 to Table 2-99 were updated. The following sections were updated: Low Power Mode, Interface, Data Registers (DRs), Security, Silicon Explorer II Probe Interface, and Programming. In the PQ208 (AX500) section, pins 2, 52, and 156 changed from VCCDA to VCCA. For pins 170 and 171, the I/O names refer to pair 23 instead of 24. The following changes were made in the FG676 (AX500) section: AE2, AE25 Change from NC to GND. AF2, AF25 Changed from GND to NC AB4, AF24, C1, C26 Changed from VCCDA to VCCA AD15 Change from VCCDA to VCOMPLE AD17 Changed from VCOMPLE to VCCDA In the FG896 (AX2000) section, the AK28 changed from VCCIB5 to VCCIB4. The CQ352 and CG624 sections are new.
7.0	—	The following is the list of changes in revision 7.0 of the document: All I/O FIFO capability was removed. Table 3-1 was updated. Figure 1-9 was updated. Figure 2-5 was updated. The Using an I/O Register section was updated. The AX250 and AX1000 descriptions were added to the FG484 section.
6.0	—	The following is the list of changes in revision 6.0 of the document: Table 2-3 was updated. Figure 2-1 was updated. Figure 2-49 was updated. Figure 2-53 was updated.
5.0	—	The following is the list of changes in revision 5.0 of the document: In the PQ208 table, pin 196 was missing, but it has been added in this version with a function of GND. The following pins in the FG484 table for AX500 were changed: Pin G7 is GND/LP Pins AB8, C10, C11, C14, AB16 are NC. The FG676 table was updated.
4.0	—	The following is the list of changes in revision 4.0 of the document: The Device Resources section was updated for the CS180. The Programmable Interconnect Element and Figure 1-2 are new. The "CS180" table is new. The PQ208 tables for the AX500 were updated. The following pins were not defined in the previous version: GND 21 IO106PB5F10/CLKHP 71 GND 136
3.0	—	The following is the list of changes in revision 3.0 of the document: Table 3-1, Ordering Information, Device Resources, and the Product Plan table were updated. The following figures and tables were updated: Figure 1-3 Figure 1-8 Table 2-3 Table 2-13 Figure 2-2 Figure 2-11 The Design Environment section was updated. The Package Thermal Characteristics was updated. The timing characteristics tables fromTable 2-27 to Table 2-68 were updated. The Global Resources section was updated. The timing characteristics tables from Table 2-102 and Table 2-103 were updated. The PQ208, FG256, and FG324 tables are new.