Jump to main content
Axcelerator Family FPGAs Datasheet
Search
Home
2
Electrical Specifications
2.11
Other Architectural Features
2.11.4
Special Fuses
Introduction
1
General Description
2
Electrical Specifications
2.1
Operating Conditions
2.2
Thermal Characteristics
2.3
I/O Specifications
2.4
Voltage-Referenced I/O Standards
2.5
Differential Standards
2.6
Module Specifications
2.7
Routing Specifications
2.8
Global Resources
2.9
Axcelerator Clock Management System
2.10
Embedded Memory
2.11
Other Architectural Features
2.11.1
Low Power Mode
2.11.2
JTAG
2.11.3
Interface
2.11.4
Special Fuses
2.11.4.1
Security
2.11.4.2
Global Set Fuse
2.11.5
Silicon Explorer II Probe Interface
2.12
Programming
3
Package Pin Assignments
4
Revision History
Microchip FPGA Support
Microchip Information
2.11.4 Special Fuses
(Ask a Question)
