8 PERFORMANCE

Effective Endurance:

Determining effective endurance is not a trivial calculation because it is dependent on many factors. Traditionally, endurance is defined as the number of times a single address can be safely written. This definition does not apply to emulated data EEPROM for a few different reasons.

First, writing a data EEPROM address five times does not mean five erase/write cycles of endurance were consumed. From the perspective of the program memory, five writes were made to five different program memory addresses. These five writes will not cost any additional endurance cycles until the page is filled and the pack routine is called.

Second, calculating effective endurance is more than simply multiplying program memory page size and the size of the emulated data EEPROM. The entire page is not available for emulation. The page status information is stored in the beginning of the page, which is one location of program memory for the algorithm. In addition, more locations will be consumed after the pack routine depending on how many data EEPROM addresses were written. As a result, writing an address once has a significant impact to endurance because one less location is available after the array is packed.

Based on the discussion to this point, a simplified equation, Equation-1 can be made for total effective endurance. For more information on the terms, refer to “Definition of Terms”.

Working through an example for the dsPIC33AK128MC106, this device has a 1024-instructions words page. The DEE algorithm reserves one location for page status.

Equation-2 provides the formula for calculating two pages of program memory, 10 locations of emulated data EEPROM and the typical endurance limit.

An average effective endurance can be calculated by dividing the total effective endurance by the size of the emulated data EEPROM bank, but this does not tell the whole story. It assumes that every data EEPROM address is updated at the same rate. In most applications, this is not true. Some data, such as calibration data or user information, may be rarely updated, while sensor information can be written more frequently. Addresses written more often will consume a greater amount of program memory endurance. Therefore, how writes are distributed across the data EEPROM addresses significantly affects effective endurance. Ratios could be assigned to each address to create a more accurate calculation, but this is still only an approximation. It is difficult to predict how often each address will be written during an application’s lifetime.

EQUATION 1: EFFECTIVE ENDURANCE

Calculated Total Effective endurance = (Page Size – Page Status Size – Maximum Data EE Size Per Bank) x Number of Pages Flash Pages Per EEPROM Bank x Requested Total Effective Endurance.

EQUATION 2: EFFECTIVE ENDURANCE CALCULATION EXAMPLE

Calculated Total Effective endurance = (256 – 1 – 10) x 2 x 1000 = 490,000 Cycles

Note: In devices with ECC and minimum word write size is quad word (4 words), the flash page size to be used for calculation should be (flash page size /4) because the hardware has one ECC per 4 instruction words, but DEE operate at 2 instructions word level, one instruction to store DEE address and one instruction to store DEE Data, remaining 2 instructions are unused. So for devices with ECC and quad word instruction write, DEE effectively uses only one instruction to store the data , So effective Page size would be one fourth of the actual page size.