3 THEORY OF OPERATION

The algorithm in this application note supports selectable, multiple emulated data EEPROM banks with a total size of up to multiples of "Maximum Data EE Size" locations, with a single address space, ranging from 0 to the total size of the emulated data EEPROM’s minus one (see the below note).

For example, if the implemented size of the data EEPROM is five, and two data EEPROM banks are used, only the addresses in the range, 0 to 9, are available.

Note: dsPIC implementations support multiple EEPROM banks. Each EEPROM can have a maximum of 255 addresses(This is not always true , please check the value of Maximum Data EE Size Per Bank for the given device). Therefore, the total addresses are from 0 to N x 255 – 1, where N = the number of EEPROM banks.