4.2 Open Loop with Current Limit (PWM+COG+CMP+PRG+FVR) Mode

The current limit is simulated by adding another falling source to the COG module. This falling source is derived from the comparator CMP output. The CMP controls the duty cycle by comparing the input current sense signal from the current transformer to a reference level set by the fixed voltage reference (FVR). The reference signal is slope-compensated before being fed to the comparator by adding a negative ramp to the FVR using the Programmable Ramp Generator (PRG). The figure below shows the block diagram of the open loop configuration.