4.4 VMC Closed Loop Mode

Voltage Mode Control is established by closing the voltage feedback loop through an error amplifier and analog ramp comparator CMP.

The voltage loop uses an on-chip Operational Amplifier (OPA) as differential error amplifier, comparing the output voltage feedback signal against an internal reference voltage. This reference voltage is applied by DAC, which is configured and set by firmware. The inverting input and output of the error amplifier are routed to device pins to insert an external RC compensation filter into the amplifier feedback loop.

The PRG is configured to produce a positive sawtooth waveform, which is synchronized and driven by the digital PWM generator. The peak voltage of the sawtooth is determined by the switching frequency and user-selected slew rate of the ramp voltage. An analog comparator is used to compare the PRG sawtooth waveform against the error amplifier output signal (reference). The comparator output is further routed into the PWM output generator logic COG, truncating the active on-time when the PRG sawtooth ramp exceeds the error amplifier reference signal level. The COG logic performs the function of an SR latch, preventing undesired resets until the end of the switching period.

In this setup, the digital PWM module is determining the switching period and maximum duty ratio at which the active on-time will be terminated in case the COG has not been tripped by the ramp generator comparator.