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32-bit Arm Cortex-M0+ with 5V Support, CAN-FD, PTC, and Advanced Analog
32-bit Arm Cortex-M0+ with 5V Support, CAN-FD, PTC, and Advanced Analog
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ATSAMC20N17A ATSAMC20N18A ATSAMC21E15A ATSAMC21N17A ATSAMC21N18A ATSAMC20E15A ATSAMC20E16A ATSAMC20E17A ATSAMC20E18A ATSAMC20G15A ATSAMC20G16A ATSAMC20G17A ATSAMC20G18A ATSAMC20J15A ATSAMC20J16A ATSAMC20J17A ATSAMC20J18A ATSAMC21E16A ATSAMC21E17A ATSAMC21E18A ATSAMC21G15A ATSAMC21G16A ATSAMC21G17A ATSAMC21G18A ATSAMC21J15A ATSAMC21J16A ATSAMC21J17A ATSAMC21J18A
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  2. 33 SERCOM I2C – Inter-Integrated Circuit
  3. 33.6 Functional Description
  4. 33.6.2 Basic Operation
  5. 33.6.2.4 I2C Host Operation
  6. 33.6.2.4.1 Host Clock Generation
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  • Features
  • 1 Configuration Summary
  • 2 Ordering Information
  • 3 Block Diagram
  • 4 Pinout
  • 5 Signal Descriptions List
  • 6 I/O Multiplexing and Considerations
  • 7 Power Supply and Start-Up Considerations
  • 8 Product Mapping
  • 9 Memories
  • 10 Processor and Architecture
  • 11 PAC - Peripheral Access Controller
  • 12 Peripherals Configuration Summary
  • 13 DSU - Device Service Unit
  • 14 DIVAS – Divide and Square Root Accelerator
  • 15 Clock System
  • 16 GCLK - Generic Clock Controller

  • 17 MCLK – Main Clock
  • 18 RSTC – Reset Controller
  • 19 PM - Power Manager
  • 20 OSCCTRL – Oscillators Controller
  • 21 OSC32KCTRL – 32.768 kHz Oscillators Controller
  • 22 SUPC – Supply Controller
  • 23 WDT – Watchdog Timer
  • 24 RTC – Real-Time Counter
  • 25 DMAC – Direct Memory Access Controller
  • 26 EIC – External Interrupt Controller
  • 27 NVMCTRL – Nonvolatile Memory Controller
  • 28 PORT - I/O Pin Controller
  • 29 Event System (EVSYS)
  • 30 SERCOM – Serial Communication Interface
  • 31 SERCOM USART - SERCOM Synchronous and Asynchronous Receiver and Transmitter
  • 32 SERCOM SPI – SERCOM Serial Peripheral Interface
  • 33 SERCOM I2C – Inter-Integrated Circuit
    • 33.1 Overview
    • 33.2 Features
    • 33.3 Block Diagram
    • 33.4 Signal Description
    • 33.5 Product Dependencies
    • 33.6 Functional Description
      • 33.6.1 Principle of Operation
      • 33.6.2 Basic Operation
        • 33.6.2.1 Initialization
        • 33.6.2.2 Enabling, Disabling, and Resetting
        • 33.6.2.3 I2C Bus State Logic
        • 33.6.2.4 I2C Host Operation
          • 33.6.2.4.1 Host Clock Generation
            • 33.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
            • 33.6.2.4.1.2 Host Clock Generation (High-Speed Mode)
          • 33.6.2.4.2 Transmitting Address Packets
          • 33.6.2.4.3 Transmitting Data Packets
          • 33.6.2.4.4 Receiving Data Packets (SCLSM=0)
          • 33.6.2.4.5 Receiving Data Packets (SCLSM=1)
          • 33.6.2.4.6 High-Speed Mode
          • 33.6.2.4.7 10-Bit Addressing
        • 33.6.2.5 I2C Client Operation
      • 33.6.3 Additional Features
      • 33.6.4 DMA, Interrupts and Events
      • 33.6.5 Sleep Mode Operation
      • 33.6.6 Synchronization
    • 33.7 Register Summary - I2C Client
    • 33.8 Register Description - I2C Client
    • 33.9 Register Summary - I2C Host
    • 33.10 Register Description - I2C Host
  • 34 CAN - Control Area Network (SAM C21 Only)
  • 35 Timer/Counter (TC)
  • 36 Timer/Counter for Control Applications (TCC)
  • 37 Configurable Custom Logic (CCL)
  • 38 ADC - Analog-to-Digital Converter
  • 39 SDADC – Sigma-Delta Analog-to-Digital Converter (SAM C21 only)
  • 40 AC – Analog Comparators
  • 41 DAC – Digital-to-Analog Converter (SAM C21 only)
  • 42 Peripheral Touch Controller (PTC)
  • 43 TSENS – Temperature Sensor
  • 44 FREQM – Frequency Meter
  • 45 Electrical Characteristics 85°C (SAM C20/C21 E/G/J)
  • 46 Electrical Characteristics 105°C (SAM C20/C21 E/G/J)
  • 47 Electrical Characteristics 105°C (SAM C20/C21 N)
  • 48 Electrical Characteristics AEC - Q100 Grade 1, 125°C (SAM C20/C21 E/G/J)
  • 49 Electrical Characteristics AEC - Q100 Grade 1, 125°C (SAM C20/C21 N)
  • 50 Appendix A
  • 51 Appendix B
  • 52 Packaging Information
  • 53 Schematic Checklist
  • 54 Revision History
  • 55 Product Identification System
  • Microchip Information

33.6.2.4.1 Host Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:
  • Standard mode (Sm) up to 100 kHz
  • Fast mode (Fm) up to 400 kHz
  • Fast mode Plus (Fm+) up to 1 MHz
  • High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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