48.8.3 Digital Phase Locked Loop (DPLL) Characteristics

Table 48-27. Digital Phase Locked Loop Characteristics
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
fIN ⁽¹⁾	Input frequency		32	-	2000	KHz
fOUT ⁽¹⁾	Output frequency		48	-	96	MHz
Jp ⁽²⁾	Period jitter (Peak-Peak value)	fIN= 32 kHz, fOUT= 48 MHz	-	1.5	4.0	%
		fIN= 32 kHz, fOUT= 96 MHz	-	2.7	10.0
		fIN= 2 MHz, fOUT= 48 MHz	-	1.8	5.0
		fIN= 2 MHz, fOUT= 96 MHz	-	2.5	8.0
tLOCK ⁽²⁾	Lock Time	After startup, time to get lock signal. fIN= 32 kHz, fOUT= 96 MHz	-	1.1	1.6	ms
tLOCK ⁽²⁾	Lock Time	After startup, time to get lock signal. fIN= 2 MHz, fOUT= 96 MHz	-	25	40	µs
Duty ⁽¹⁾	Duty cycle		-	50	-	%

These values are based on simulation. These values are not covered by test limits in production or characterization.
These values are based on characterization.

Table 48-28. Power Consumption⁽¹⁾
Symbol	Parameters	Conditions	Ta	Typ.	Max	Units
IDD	Current Consumption	Ck=48MHz, VDD=5.0V	Max 125°C Typ 25°C	536	693	µA
IDD	Current Consumption	Ck=96MHz, VDD=5.0V	Max 125°C Typ 25°C	865	1048	µA