19.4.3.2 Channel Suspend

The channel operation can be suspended at any time by software by writing to the Suspend command in the Command bit field of Channel Control B register (CHCTRLB.CMD = 0x01). After the ongoing beat transfer is completed, the channel operation is suspended and CHCTRLB.CMD is automatically cleared.

When suspended, the Channel Suspend Interrupt flag in the Channel Interrupt Status and Clear register is set (CHINTFLAG.SUSP = 1), and the optional suspend interrupt is generated.

By configuring the block action to suspend by writing to the Block Action bit field in the Block Transfer Control register (BTCTRL.BLOCKACT is 0x2 or 0x3), the DMA channel will be suspended after it has completed a block transfer. The DMA channel will remain enabled and able to receive transfer triggers, but it will be removed from the arbitration scheme.

If an invalid transfer descriptor (BTCTRL.VALID = 0) is fetched from SRAM, the DMA channel will be suspended, and the Channel Fetch Error bit in the Channel Status (CHASTATUS.FERR) register will be set.

Note: Only enabled DMA channels can be suspended. If a channel is disabled when a suspend command is issued, the internal suspend command will be ignored.

Refer to the Transfer Descriptors section for more details on transfer descriptors.