6.5.7.1.3 Write SRAM

Table 6-20. Write SRAM Sequence
Steps	rddi_dap
Clear sticky bits	`WriteDP(DP_ABORT, (ORUNERRCLR \| WDERRCLR \| STKERRCLR \| STKCMPCLR))`
Select BANK0	`WriteDP(DP_SELECT, MEMAP_BANK_0)`
Set access	`WriteAP(MEM_AP_CSW, (SIZE32 \| SADDRINC \| HPROT[3] \| RESERVED \| MSTRDBG))` Access size: 32-bit Single Address Increment User/Privilege Control (read-only) Master type: Debug
<outer loop>
Write Address to the Transfer Address Register (TAR)	`WriteAP(MEM_AP_TAR, Address)`
Write data to the device	`WriteAP(MEM_AP_DRW, Value)`
<end outer loop>

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