19.7.1 Block Transfer Control

This bit field selects the step size of the address increment. The setting applies to the to source or destination address, depending on the STEPSEL setting.

This bit controls if the source or destination addresses are using the step size settings.

This bit controls whether the destination address increments between beat transfers or not. When this bit is set, the destination address is by default incremented by one beat size in byte(s). If the STEPSEL bit is ‘0’, the STEPSIZE register will control the size of the increments.

This bit controls whether the source address increments between beat transfers or not. When this bit is set, the source address is by default incremented by one beat size in byte(s). If the STEPSEL bit is ‘1’, the STEPSIZE register will control the size of the increments.

This bit field controls the size of one beat. A beat is the size of one data transfer bus access, and the setting applies to both read and write accesses.

This bit field controls what actions the DMAC will take after a block transfer has completed.

This bit field controls the event output selection.

Writing a ‘0’ to this bit in the Descriptor or Write-Back memory will suspend the DMA channel operation when fetching the corresponding descriptor.

The bit is automatically cleared in the Write-Back memory section when the channel is aborted, when an error is detected during the block transfer, or when the block transfer is completed.