4.4.2 Configuration

Table 4-4. Bus Matrix Hosts

Hosts (HSRAM)
Cortex M0+ Processor (CM0+)
Device Service Unit (DSU)
Direct Memory Access Controller/Data Access (DMAC)

Table 4-5. Bus Matrix Clients

Bus Matrix Clients
Internal Flash Memory
SRAM - CM0+ Access
SRAM - DSU Access
AHB-APB Bridge A
AHB-APB Bridge B
AHB-APB Bridge C
SRAM - DMAC Data Access

Table 4-6. SRAM Port Connections

SRAM Port Connection	Port ID	Connection Type
Cortex M0+ (CM0+) Processor	0	Bus Matrix
Device Service Unit (DSU)	1	Bus Matrix
Direct Memory Access Controller (DMAC) - Data Access	2	Bus Matrix
Direct Memory Access Controller (DMAC) - Fetch Access 0	3	Direct
Direct Memory Access Controller (DMAC) - Fetch Access 1	4	Direct
Direct Memory Access Controller (DMAC) - Write-Back Access 0	5	Direct
Direct Memory Access Controller (DMAC) - Write-Back Access 1	6	Direct
Reserved	7
Reserved	8
Micro Trace Buffer (MTB)	9	Direct