18.5.3 Clocks
The DSU bus clocks (CLK_DSU_AHB and CLK_DSU_APB) can be enabled and disabled in the MCLK - Main Clock controller. By default, these clocks are enabled, so the DSU will be operational.
The DSU bus clocks (CLK_DSU_AHB and CLK_DSU_APB) can be enabled and disabled in the MCLK - Main Clock controller. By default, these clocks are enabled, so the DSU will be operational.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.