18.5.4 DMA

The DSU generates the following DMA request:

• Debug Communication Channel n (DCCn): The request is set when the DCCn register is read. The request is cleared when the DCCn register is written. This behavior can be inverted by setting the DMA Trigger Level bit in the Control B (CTRLB.DCCDMALVLn) register.

The DMA request lines are connected to the DMA Controller (DMAC). The DMAC must be configured before using the DSU’s DMA requests.

Refer to the DMAC – Direct Memory Access Controller chapter for details.