30.4.2.4 SPI Transfer Modes
There are four combinations of SCK phase and polarity for transferring serial data. The SPI data transfer modes are shown in Table 30-2 and Figure 30-3.
SCK phase is configured by the Clock Phase bit in the CTRLA register (CTRLA.CPHA). SCK polarity is programmed by the Clock Polarity bit in the CTRLA register (CTRLA.CPOL). Data bits are shifted out and latched in on opposite edges of the SCK signal. This ensures sufficient time for the data signals to stabilize.
| Mode | CPOL | CPHA | Leading Edge | Trailing Edge |
|---|---|---|---|---|
| 0 | 0 | 0 | Rising, sample | Falling, setup |
| 1 | 0 | 1 | Rising, setup | Falling, sample |
| 2 | 1 | 0 | Falling, sample | Rising, setup |
| 3 | 1 | 1 | Falling, setup | Rising, sample |
Note:
Leading edge is the first clock edge in a clock cycle.
Trailing edge is the second clock edge in a clock cycle.
