6.5.4.4 CPU Reset Extension

The DSU peripheral has CPU Reset and Boot ROM extension mechanisms that allow a debugger to be connected while preventing the CPU from starting execution of the customer application. This is also known as debugger cold-plugging.

This feature requires the debugger to control the SWCLK and RESET pins. The debugger forces a CPU Reset extension by driving three pulses on SWCLK when the RESET pin is low.

The main purpose of the CPU Reset extension is to avoid executing potentially corrupted code at the boot and to provide a safe way to connect to a device without making any assumptions about its current state. Combined with the Boot ROM Reset extension, the debugger controls the behavior of the Boot ROM Interactive and Park modes. This allows reading and writing of the memory and peripherals without CPU interference.

After the initial connection sequence, the debugger must control the CPU Reset and Boot ROM extension to maneuver the Boot ROM into Interactive or Park modes. Typically, Park mode is used to program the device using the ARM DAP AHB-AP port.

The CPU Reset Extension (bit 8) and Boot ROM Extension (bit 16) are located in the DSU Status A (DSU.STATUSA) register @0x4100_2104. Each of these bits can be cleared by writing a ‘1’ to them. To release the CPU, write a ‘1’ to the CRSTEXT0 bit in the STAUSA (STATUSA.CRSTEXT0) register. The BREXT0 bit in the STATUSA (STATUSA.BREXT0) register is typically written or left untouched within the same write operation, depending on whether entry into Interactive mode or Park mode is required. Writing a ‘0’ to these bits has no effect.