20.5.3 Clocks

The WDT bus clock (CLK_WDT_APB) can be enabled or disabled in the main clock. See the Peripheral Clock Masking section in the MCLK – Main Clock chapter for more information.

A 1.024 kHz oscillator clock (CLK_WDT_OSC) is required to clock the WDT internal counter.

The CLK_WDT_OSC clock is sourced from the internal 32.768 kHz Oscillator (OSC32K).

The CLK_WDT_OSC clock is asynchronous to the bus clock (CLK_WDT_APB). Due to this asynchronicity, writes to certain registers require synchronization between the clock domains. Refer to the Synchronization section for further details.