29.4.2.4.2 Error Bits

The USART receiver has three error bits in the Status (STATUS) register: Frame Error (FERR), Buffer Overflow (BUFOVF), and Parity Error (PERR). When an error occurs, the corresponding error bit is set and remains set until it is cleared by writing ‘1’’to it. These bits are also cleared automatically when the receiver is disabled.

There are two methods for buffer overflow notification, selected by the Immediate Buffer Overflow Notification bit in the Control A register (CTRLA.IBON):

When CTRLA.IBON is set to ‘1’, the STATUS.BUFOVF flag is triggered immediately upon a buffer overflow. At this point, software can clear the receive FIFO by reading from RxDATA until the Receiver Complete Interrupt flag (INTFLAG.RXC) is cleared.

When CTRLA.IBON is set to ‘0’, the Buffer Overflow condition is indicated while data are still being received through the FIFO. After the received data are read, the STATUS.BUFOVF and INTFLAG.ERROR flags will be set, along with the Receiver Complete Interrupt flag INTFLAG.RXC.