31.5.5 Interrupts

The interrupt request line, also known as the interrupt vector, is connected to the interrupt controller. To use SERCOM I²C interrupts, the interrupt controller must be configured in advance, including enabling the interrupt line globally. For further information, refer to the NVIC - Nested Vectored Interrupt Controller section.

Each interrupt source has an interrupt flag which is in the Interrupt Flag Status and Clear (INTFLAG) register. The flag is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a ‘1’ to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a ‘1’ to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register.

An interrupt request is generated when the interrupt flag is set and the corresponding interrupt source is enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or the peripheral is reset. Refer to the INTFLAG register description for details on how to clear interrupt flags.

All interrupt requests from the peripheral are ORed together on system level to generate a single combined interrupt request to the NVIC. Therefore, the INTFLAG register must be read to determine what the interrupt condition is.

The I²C client has the following interrupt sources.

Table 31-2. Available Interrupt Vectors and Sources - I2C Client
Vector Name	Source Name	Condition	Dependency
SERCOMn	DRDY	Data Ready
	AMATCH	Address Match
	PREC	Stop Received
	ERROR	Error	The Client SCL Low Extend Time-out, SCL Low Time-out, Transmit Collision, and Bus Error bits in the Status register (STATUS.SEXTTOUT, STATUS.LOWTOUT, STATUS.COLL and STATUS.BUSERR).

The I²C host has the following interrupt sources.

Table 31-3. Available Interrupt Vectors and Sources - I2C Host
Vector Name	Source Name	Condition	Dependency
SERCOMn	SB	Client on Bus
	MB	Host on Bus
	ERROR	Error	The Transaction Length Error, Client SCL Low Extend Time-out, Host SCL Low Extend Time-out, SCL Low Time-out, Arbitration Lost, and Bus Error bits in the Status register (STATUS.LENERR, STATUS.SEXTTOUT, STATUS.MEXTTOUT, STATUS.LOWTOUT, STATUS.ARBLOST and STATUS.BUSERR).