15.4.4.3 Power Sequencing

The system supports the following power ramp scenarios for MVIO when configured in Dual Supply mode:
  • Supply ramp of VDD (VDDIO) before VDDIO2
  • Supply ramp of VDDIO2 before VDD (VDDIO)
  • VDD (VDDIO) loses and regains power
  • VDDIO2 loses and regains power

When either voltage domain loses power, the MVIO I/O pins are tri-stated. The pins will reload the current configuration of the PORT registers if VDDIO2 regains power. If VDD (VDDIO) loses power, the device will reset, and all PORTs must be reinitialized. Refer to the Electrical Characteristics section for VDD and VDDIO2 power supply thresholds.

If configured, an interrupt can be triggered either when the voltage drops below the threshold or when the voltage is restored, but never on both. The interrupt is triggered only in Dual Power mode and with VDDIO2 configured in Low-Power mode, meaning the voltage monitors are disabled.

Note:

When a peripheral is connected to the MVIO pins, it will continue to operate when the pins are tri-stated. Monitor the VDDIO2 OK (STATUS.VDDIO2OK) flag to ensure the correct operation of the peripheral and I/O pins.