Introduction

The Sigma-Delta Analog-to-Digital Converter (SDADC) converts analog signals into digital values. The SDADC has 16-bit resolution at 1 ksps and is capable of converting up to 1.5 Msps divided by the data Over Sampling Ratio (OSR).

The input selection has up to three differential analog channels. The SDADC provides signed results. ADC measurements can be started by either application software or an incoming event from another peripheral in the device. ADC measurements can be started with predictable timing and without software intervention. The SDADC also integrates a Sleep mode and a conversion sequencer. These features reduce power consumption and processor intervention. A set of reference voltages are generated internally.

This document describes the SDADC in the ATSAMC21N device is configured in differential mode and the SDADC results are displayed on a console. It also provides example code for both interrupt and polling methods, developed using MPLAB^® X IDE and MPLAB Code Configurator for reference.

Features

• Sigma-Delta converter with 16-bit resolution at 1 ksps
  • Three external analog differential input pairs
• Conversion range 0V to a wide range of VREF options
  • Hardware gain, offset, and shift compensation